EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

DTS20N17-35XB [V001]

Description
HERM RECP
CategoryThe connector   
File Size856KB,17 Pages
ManufacturerTE Connectivity
Websitehttp://www.te.com
Download Datasheet Parametric View All

DTS20N17-35XB [V001] Overview

HERM RECP

DTS20N17-35XB [V001] Parametric

Parameter NameAttribute value
Connector Systemline to panel, line to panel
Sealableyes
Connectors and terminals terminate toWires and cables
Housing sizeE (17)
Connector typesquare flange
Number of Positions55
Number of power supply locations0
Number of signal positions55
Pre-installedno
Shell plating materialElectroplated nickel
Shell materialStainless steel
Insulation MaterialsGlass
Sealedyes
Contact Current Rating (Max) (A)5
reverse polaritystandard
Terminal layout17 – 35
Terminal typeeyelet pin
polar codeB
Joint alignment typekeying
Joint fixation typeThread
Location monitoring
Cable size (AWG)22
Working group temperature range-65 – 200 °C [ -85 – 392 °F ]
Circuit ApplicationSignal
High output current high drive capability op amp
High output current high drive capability op amp...
wangwei20060608 RF/Wirelessly
Comparison of JMP and Minitab: Simple Regression Analysis
Last time, I saw someone compare JMP and Minitab based on the application of "basic statistical analysis", and concluded that JMP is far superior to Minitab in terms of statistical professionalism and...
wkhccie Embedded System
TI Labs
Our laboratory applied for "TI laboratory" last month, but the results have not come out yet. Does anyone know how long it will take to get the results? Thank you...
450678797 Microcontroller MCU
Arrow SoC Kit Study Notes
[i=s]This post was last edited by luweixuancl on 2014-12-13 12:15[/i]...
luweixuancl FPGA/CPLD
Pads are laid copper, but vias are disconnected
Somehow, a situation suddenly occurred. The PCB I drew before had been copper-plated. A via network was the ground. Its front and back sides were connected to the copper foil through flower holes. Eve...
ienglgge PCB Design
I'm begging for a tutorial video on sequential logic. I can't stand reading the documentation...
I always feel that I don't understand sequential logic thoroughly, it's so painful... I personally prefer to learn through videos, I will feel sleepy when reading materials{:1_101:} Dear experts passi...
你不懂我伤悲 FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2059  2597  2772  2530  1033  42  53  56  51  21 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号