Data
Sheet
FEATURES
Synchronous Buck Controller with
Constant On Time and Valley Current Mode
ADP1878/ADP1879
TYPICAL APPLICATIONS CIRCUIT
V
IN
= 2.95V TO 20V
VIN
C
C
R
C
V
REG
V
OUT
C
C2
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current sense resistor required
Power saving mode (PSM) for light loads (ADP1879 only)
Resistor programmable current limit
Power good with internal pull-up resistor
Externally programmable soft start
Thermal overload protection
Short-circuit protection
Standalone precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged output
Available in a 14-lead LFCSP_WD package
ADP1878/
ADP1879
COMP
EN
FB
GND
VREG
PGOOD
RES
PGND
SS
BST
DRVH
SW
DRVL
C
BST
C
IN
Q1
10kΩ
R
TOP
R
BOT
L
V
OUT
C
OUT
Q2
LOAD
C
VREG2
C
VREG
R
RES
R
PGD
C
SS
V
EXT
Figure 1.
APPLICATIONS
Telecommunications and networking systems
Mid-to-high end servers
Set-top boxes
DSP core power supplies
GENERAL DESCRIPTION
The
ADP1878/ADP1879
are versatile current-mode, synchronous
step-down controllers. They provide superior transient response,
optimal stability, and current-limit protection by using a constant
on time, pseudo fixed frequency with a programmable current-limit,
current control scheme. These devices offer optimum performance
at low duty cycles by using a valley, current-mode control architec-
ture allowing the
ADP1878/ADP1879
to drive all N-channel power
stages to regulate output voltages to as low as 0.6 V.
The
ADP1879
is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the ADP1879 Power Saving Mode (PSM) section for
more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz) plus the PSM option, the
ADP1878/ADP1879
are well
suited for a wide range of applications that require a single input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal low dropout regulator (LDO). In
addition, soft start programmability is included to limit input
inrush current from the input supply during startup and to
provide reverse current protection during precharged output
Rev. B
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Trademarks and registered trademarks are the property of their respective owners.
conditions. The low-side current sense, current gain scheme and
integration of a boost diode, together with the PSM/forced
pulse-width modulation (PWM) option, reduce the external
device count and improve efficiency.
The
ADP1878/ADP1879
operate over the −40°C to +125°C
junction temperature range and are available in a 14-lead
LFCSP_WD package.
100
95
90
85
80
EFFICIENCY (%)
V
IN
= 5V (PSM)
75
70
65
60
55
50
45
40 V
IN
= 16.5V (PSM)
35
30
25
10
100
V
IN
= 13V (PSM)
T
A
= 25°C
V
OUT
= 1.8V
f
SW
= 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
1k
LOAD CURRENT (mA)
10k
100k
09441-102
V
IN
= 16.5V
V
IN
= 13V
Figure 2.
ADP1878/ADP1879
Efficiency vs. Load Current (V
OUT
= 1.8 V, 300 kHz)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
09441-001
ADP1878/ADP1879
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ....................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 17
Block Diagram ............................................................................ 17
Startup .......................................................................................... 18
Soft Start ...................................................................................... 18
Precision Enable Circuitry ........................................................ 18
Undervoltage Lockout ............................................................... 18
On-Board Low Dropout (LDO) Regulator ............................. 18
Thermal Shutdown ..................................................................... 19
Programming Resistor (RES) Detect Circuit.......................... 19
Valley Current-Limit Setting .................................................... 19
Hiccup Mode During Short Circuit ......................................... 21
Synchronous Rectifier ................................................................ 21
ADP1879 Power Saving Mode (PSM) ...................................... 21
Timer Operation ......................................................................... 22
Data
Sheet
Pseudo Fixed Frequency............................................................ 22
Power-Good Monitoring ........................................................... 23
Applications Information .............................................................. 24
Feedback Resistor Divider ........................................................ 24
Inductor Selection ...................................................................... 24
Output Ripple Voltage (ΔV
RR
) .................................................. 24
Output Capacitor Selection....................................................... 24
Compensation Network ............................................................ 25
Efficiency Consideration ........................................................... 26
Input Capacitor Selection .......................................................... 27
Thermal Considerations............................................................ 27
Design Example .......................................................................... 29
External Component Recommendations .................................... 31
Layout Considerations ................................................................... 33
IC Section (Left Side of Evaluation Board) ............................. 35
Power Section ............................................................................. 35
Differential Sensing .................................................................... 36
Typical Application Circuits ......................................................... 37
12 A, 300 kHz High Current Application Circuit .................. 37
5.5 V Input, 600 kHz Current Application Circuit ................ 37
300 kHz High Current Application Circuit ............................ 38
Packaging and Ordering Information ......................................... 39
Outline Dimensions ................................................................... 39
Ordering Guide .......................................................................... 40
REVISION HISTORY
9/12—Rev. A to Rev. B
Changes to Table 7 ...........................................................................20
6/12—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 3
7/11—Revision 0: Initial Version
Rev. B | Page 2 of 40
Data
Sheet
SPECIFICATIONS
ADP1878/ADP1879
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
BST − SW = VREG − V
RECT_DROP
(see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for T
J
= −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range
Symbol
VIN
Test Conditions/Comments
C
VIN
= 22 µF(25 V rating) right at Pin 1 to PGND (Pin 11)
ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz)
ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz)
ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz)
FB = 1.5 V, no switching
EN < 600 mV
Rising VIN (see Figure 35 for temperature variation)
Falling VIN from operational state
Do not load VREG externally because it is intended to
bias internal circuitry only
C
VREG
= 4.7 µF to PGND, 0.22 µF to GND, V
IN
= 2.95 V to 20 V
ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz)
ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz)
ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz)
V
IN
= 7 V, 100 mA
V
IN
= 12 V, 100 mA
0 mA to 100 mA, V
IN
= 7 V
0 mA to 100 mA, V
IN
= 20 V
V
IN
= 7 V to 20 V, 20 mA
V
IN
= 7 V to 20 V, 100 mA
100 mA out of VREG, V
IN
≤ 5 V
V
IN
= 20 V
Connect external capacitor from SS pin to GND,
C
SS
= 10 nF/ms
T
J
= 25°C
T
J
= −40°C to +85°C
T
J
= −40°C to +125°C
FB = 0.6 V, EN = VREG
RES = 47 kΩ ± 1%
RES = 22 kΩ ± 1%
RES = none
RES = 100 kΩ ± 1%
Typical values measured at 50% time points with 0 nF at
DRVH and DRVL; maximum values are guaranteed by
bench evaluation
1
2.7
5.5
11
22
Min
Typ
Max
Unit
2.95
2.95
3.25
Quiescent Current
Shutdown Current
Undervoltage Lockout
UVLO Hysteresis
INTERNAL REGULATOR
CHARACTERISTICS
VREG Operational Output Voltage
I
Q_REG
+
I
Q_BST
I
REG,SD
+
I
BST,SD
UVLO
12
12
12
1.1
140
2.65
178
20
20
20
V
V
V
mA
µA
V
mV
225
VREG
VREG Output in Regulation
Load Regulation
Line Regulation
VIN to VREG Dropout Voltage
Short VREG to PGND
SOFT START
Soft Start Period Calculation
ERROR AMPLIFER
FB Regulation Voltage
2.75
2.75
3.05
4.82
4.83
5
5
5
4.981
4.982
32
34
1.8
2.0
306
229
10
600
600
600
496
1
3
6
12
24
5.5
5.5
5.5
5.16
5.16
415
320
V
V
V
V
V
mV
mV
mV
mV
mV
mA
nF/ms
mV
mV
mV
µS
nA
V/V
V/V
V/V
V/V
V
FB
Transconductance
FB Input Leakage Current
CURRENT SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from RES to PGND
G
m
I
FB, LEAK
596
594.2
320
604
605.8
670
50
3.3
6.5
13
26
SWITCHING FREQUENCY
ADP1878ACPZ-0.3-R7/
ADP1879ACPZ-0.3-R7
On Time
Minimum On Time
Minimum Off Time
300
V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C
V
IN
= 20 V
84% duty cycle (maximum)
Rev. B | Page 3 of 40
kHz
1345
190
400
ns
ns
ns
1120
1200
145
340
ADP1878/ADP1879
Parameter
ADP1878ACPZ-0.6-R7/
ADP1879ACPZ-0.6-R7
On Time
Minimum On Time
Minimum Off Time
ADP1878ACPZ-1.0-R7/
ADP1879ACPZ-1.0-R7
On Time
Minimum On Time
Minimum Off Time
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time
2
Fall Time
2
Low-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time
2
Fall Time
2
Propagation Delays
DRVL Fall to DRVH Rise
2
DRVH Fall to DRVL Rise
2
SW Leakage Current
Integrated Rectifier
Channel Impedance
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
COMP VOLTAGE
COMP Clamp Low Voltage
COMP Clamp High Voltage
COMP Zero Current Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
CURRENT LIMIT
Hiccup Current-Limit Timing
OVERVOLTAGE AND POWER-
GOOD THRESHOLDS
FB Power-Good Threshold
FB Power-Good Hysteresis
FB Overvoltage Threshold
FB Overvoltage Hysteresis
PGOOD Low Voltage During Sink
PGOOD Leakage Current
1
Data
Sheet
Symbol
Test Conditions/Comments
Min
Typ
600
540
82
340
1.0
312
52
340
Max
Unit
kHz
ns
ns
ns
MHz
ns
ns
ns
V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C
V
IN
= 20 V, V
OUT
= 0.8 V
65% duty cycle (maximum)
500
605
110
400
V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C
V
IN
= 20 V
45% duty cycle (maximum)
285
360
85
400
t
r, DRVH
t
f, DRVH
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 59)
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 60)
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
V
REG
= 5.0 V, C
IN
= 4.3 nF (see Figure 60)
V
REG
= 5.0 V, C
IN
= 4.3 nF (see Figure 59)
BST − SW = 4.4 V (see Figure 59)
BST − SW = 4.4 V (see Figure 60)
BST = 25 V, SW = 20 V, V
REG
= 5 V
I
SINK
= 10 mA
V
IN
= 2.9 V to 20 V, V
REG
= 2.75 V to 5.5 V
V
IN
= 2.9 V to 20 V, V
REG
= 2.75 V to 5.5 V
605
2.20
0.72
25
11
1.5
0.7
18
16
15.7
16
3
1
Ω
Ω
ns
ns
Ω
Ω
ns
ns
ns
ns
µA
Ω
2.2
1
t
r,DRVL
t
f,DRVL
t
tpdhDRVH
t
tpdhDRVL
I
SWLEAK
110
22.3
634
31
663
mV
mV
V
V
COMP(LOW)
V
COMP(HIGH)
V
COMP_ZCT
T
TMSD
Tie EN pin to VREG to enable device
(2.75 V ≤ V
REG
≤ 5.5 V)
(2.75 V ≤ V
REG
≤ 5.5 V)
(2.75 V ≤ V
REG
≤ 5.5 V)
Rising temperature
0.47
2.55
1.10
155
15
6
V
V
°C
°C
ms
COMP = 2.4 V
PGOOD
FB
PGD
FB
OV
V
PGOOD
V
FB
rising during system power up
V
FB
rising during overvoltage event, I
PGOOD
= 1 mA
I
PGOOD
= 1 mA
PGOOD = 5 V
542
34
691
35
143
1
566
55
710
55
200
100
mV
mV
mV
mV
mV
nA
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), C
GATE
= 4.3 nF, and the high- and low-side
MOSFETs being Infineon BSC042N03MS G.
2
Not automatic test equipment (ATE) tested.
Rev. B | Page 4 of 40
Data
Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VREG to PGND, GND
VIN, EN, PGOOD to PGND
FB, COMP, RES, SS to GND
DRVL to PGND
SW to PGND
BST to SW
BST to PGND
DRVH to SW
PGND to GND
PGOOD Input Current
θ
JA
(14-Lead LFCSP_WD)
4-Layer Board
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Maximum Soldering Lead Temperature
(10 sec)
Rating
−0.3 V to +6 V
−0.3 V to +28 V
−0.3 V to (VREG + 0.3 V)
−0.3 V to (VREG + 0.3 V)
−2.0 V to +28 V
−0.6 V to (VREG + 0.3 V)
−0.3 V to +28 V
−0.3 V to VREG
±0.3 V
35 mA
30°C/W
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
300°C
ADP1878/ADP1879
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Boundary Condition
In determining the values given in Table 2 and Table 3, natural
convection is used to transfer heat to a 4-layer evaluation board.
Table 3. Thermal Resistance
Package Type
θ
JA
(14-Lead LFCSP_WD)
4-Layer Board
θ
JA
30
Unit
°C/W
ESD CAUTION
Stresses a bove those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
Rev. B | Page 5 of 40
PCB Design
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