NXP Semiconductors
Technical Data
Document Number: MC34931
Rev. 4.0, 8/2016
5.0 A H-Bridge
The 34931 is a monolithic H-Bridge Power IC in a robust thermally enhanced
package. It is designed for any low voltage DC servo motor control application
within the current and voltage limits stated in this specification. This device is
powered by SMARTMOS technology.
The 34931 H-Bridge is able to control inductive loads with currents up to 5.0 A
peak. RMS current capability is subject to the degree of heatsinking provided to
the device package. Internal peak current limiting (regulation) is activated at load
currents above 6.5 A ±1.5 A. Output loads can be pulse-width modulated
(PWMed at frequencies up to 20 kHz. A load current feedback feature provides
a proportional (0.24% of the load current) current output suitable for monitoring
by a microcontroller’s A/D input. A status flag output reports undervoltage,
overcurrent, and overtemperature fault conditions.
Two independent inputs provide polarity control of two half-bridge totem-pole
outputs. The disable inputs are provided to force the H-Bridge outputs to tri-state
(high-impedance off-state).
Features
• 5.0 V to 36 V continuous operation with 24 V nominal operating voltage
(transient operation from 5.0 V to 40 V)
• 235 mΩ maximum R
DS(on)
at T
J
= 150 °C (each H-Bridge MOSFET)
• 3.0 V and 5.0 V TTL/CMOS logic compatible inputs
• Overcurrent limiting (regulation) via internal constant-off-time PWM
• Output short-circuit protection (short to VPWR or GND)
• Temperature-dependant current-limit threshold reduction
• All inputs have an internal source/sink to define the default (floating input)
states
• Sleep mode with current draw < 20 µA
V
DD
34931
Industrial
H-BRIDGE
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW-EP
Applications
• DC motor control
• DC brushed and servo motor driver
• Copiers, printers
• Factory automation
• POS, ATM, vending kiosks
• Robotics
• Security camera control
• Ticketing, toll systems
V
PWR
34931
SF
FB
VPWR
CCP
OUT1
IN1
IN2
OUT2
D1
EN/D2
PGND
AGND
MOTOR
MCU
Figure 1. MC34931 simplified application diagram
© 2016 NXP B.V.
1
Orderable parts
Table 1. Orderable part variations
Part number
MC34931EK
MC34931SEK
PWM frequency
11 kHz
20 kHz
Temperature (T
A
)
- 40 °C to 85 °C
Package
32 SOICW-EP
Notes
(1)
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
34931
2
NXP Semiconductors
2
Internal block diagram
VPWR
LOGIC SUPPLY
VDD
CCP
VCP CHARGE
PUMP
TO GATES
HS1
HS1
HS2
OUT1
OUT2
LS1
LS2
IN1
IN2
EN/D2
D1
SF
FB
AGND
GATE DRIVE
AND
PROTECTION
LOGIC
LS1
HS2
LS2
VSENSE
ILIM PWM
PGND
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
PGND
Figure 2. 34931 Simplified internal block diagram
34931
NXP Semiconductors
3
3
3.1
Pin connections
Pinout diagram
AGND
D1
FB
N/C
EN/D2
N/C
VPWR
VPWR
N/C
OUT1
OUT1
N/C
N/C
N/C
PGND
PGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
SF
IN1
N/C
IN2
CCP
N/C
VPWR
VPWR
N/C
OUT2
OUT2
N/C
N/C
N/C
PGND
PGND
EP
25
24
23
22
21
20
19
18
17
32 SOICW-EP
Transparent Top View
Figure 3. 34931 pin connections
A functional description of each pin can be found in the Functional Description section beginning on
page 12.
Table 2. 34931 pin definitions
Pin number
2
3
Pin name Pin function
D1
FB
Logic Input
Analog
Output
Logic Input
Formal name
Disable Input 1
(Active High)
Feedback
Definition
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger input
with ~ 80
μA
source so default condition = disabled.
The load current feedback output provides ground referenced 0.24% of the high-side
output current. (Tie to GND through a resistor if not used.)
When EN/D2 is logic HIGH the H-Bridge is operational. When EN/D2 is logic LOW,
the H-Bridge outputs are tri-stated and placed in Sleep mode. (logic input with
~ 80
μA
sink so default condition = Sleep mode.)
These pins must be connected together physically as close as possible and directly
soldered down to a wide, thick, low resistance supply plane on the PCB.
Source of HS1 and drain of LS1
High-current power ground pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low resistance ground plane on
the PCB.
Source of HS2 and drain of LS2
External reservoir capacitor connection for the internal charge pump; connected to
VPWR. Allowable values are 30 nF to 100 nF.
Note:
This capacitor is required for
the proper performance of the device.
Logic input control of OUT2;e.g., when IN2 is logic HIGH, OUT2 is set to VPWR, and
when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger Input with ~ 80
μA
source so default condition = OUT2 HIGH.)
5
EN/D2
Enable Input
Positive Power
Supply
H-Bridge Output 1
7, 8, 25, 26
10, 11
VPWR
OUT1
Power Input
Power
Output
Power
Ground
Power
Output
Analog
Output
15-18
PGND
Power Ground
22, 23
OUT2
H-Bridge Output 2
Charge Pump
Capacitor
28
CCP
29
IN2
Logic Input
Input 2
34931
4
NXP Semiconductors
Table 2. 34931 pin definitions (continued)
Pin number
31
Pin name Pin function
IN1
Logic Input
Logic Output
-
Open Drain
Analog
Ground
None
Formal name
Input 1
Definition
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to VPWR,
and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with ~ 80
μA
source so default condition = OUT1 HIGH.)
Open drain active LOW Status Flag output (requires an external pull-up resistor
to V
DD
. Maximum permissible load current < 0.5 mA. Maximum V
SFLOW
< 0.4 V
at
0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
The low-current analog signal ground must be connected to PGND via low-
impedance path (<10 mΩ, 0 Hz to 20 kHz).
Pin is not used
Exposed TAB is also the main heatsinking path for the device and must be
connected to GND.
32
SF
Status Flag
(Active Low)
Analog Signal Ground
1
4, 6, 9, 12-14,
19-21, 24, 27,
30
EP
AGND
N/C
No Connect
EP
Thermal Pad
Exposed Pad
34931
NXP Semiconductors
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