Features ................................................................................................................................................................ 6
Read Training (Only for ECP5 Device) ........................................................................................................ 8
Selecting READ_PULSE_TAP Value (Only for LatticeECP3 Device) .................................................................. 9
Data Path Logic.......................................................................................................................................... 10
Write Data Path.......................................................................................................................................... 10
Read Data Path.......................................................................................................................................... 10
Signal Descriptions ............................................................................................................................................. 10
Using the DFI ...................................................................................................................................................... 13
Command and Address ............................................................................................................................. 14
Write Data Interface ................................................................................................................................... 15
Read Data Interface ................................................................................................................................... 15
Type Tab ............................................................................................................................................................. 20
Memory Type ............................................................................................................................................. 21
Memory Data Bus Size .............................................................................................................................. 21
CAS Latency .............................................................................................................................................. 22
DLL Control for PD..................................................................................................................................... 23
ODI Control ................................................................................................................................................ 23
CAS Write Latency..................................................................................................................................... 23
PLL Used ................................................................................................................................................... 25
Design Tools Options and Info Tab..................................................................................................................... 25
Support Synplify ......................................................................................................................................... 26
Support Precision....................................................................................................................................... 26
Support ModelSim...................................................................................................................................... 26
Support ALDEC.......................................................................................................................................... 26
User I/F Pins .............................................................................................................................................. 27
Chapter 4. IP Core Generation and Evaluation
for LatticeECP3 DDR3 PHY.................................................................................................................. 28
Getting Started .................................................................................................................................................... 28
IPexpress-Created Files and Top Level Directory Structure............................................................................... 30
DDR3 PHY IP File Structure ...................................................................................................................... 32
Enabling Hardware Evaluation in Diamond................................................................................................ 34
Updating/Regenerating the IP Core .................................................................................................................... 34
Chapter 5. IP Core Generation and Evaluation for ECP5 DDR3 PHY............................................... 36
Getting Started .................................................................................................................................................... 36
Created Files and Top Level Directory Structure ................................................................................................ 39
DDR3 PHY IP File Structure ...................................................................................................................... 41
Simulation Files for IP Evaluation .............................................................................................................. 43
Enabling Hardware Evaluation in Diamond................................................................................................ 45
Regenerating/Recreating the IP Core ................................................................................................................. 45
Regenerating an IP Core in Clarity Designer Tool ..................................................................................... 45
Recreating an IP Core in Clarity Designer Tool ......................................................................................... 46
FREQUENCY Preferences ........................................................................................................................ 47
MAXDELAY NET ....................................................................................................................................... 47
Dummy Logic in IP Core Evaluation ................................................................................................................... 48
Top-level Wrapper File Only for Evaluation Implementation...................................................................... 48
Top-level Wrapper file for All Simulation Cases and Implementation in a User Design............................. 49
E-mail Support ........................................................................................................................................... 51
Local Support ............................................................................................................................................. 51
Internet ....................................................................................................................................................... 51
Revision History .................................................................................................................................................. 51
Appendix A. Resource Utilization ....................................................................................................... 52
Ordering Part Number................................................................................................................................ 52
Ordering Information ........................................................................................................................................... 53
Appendix B. Lattice Devices Versus................................................................................................... 54
Appendix C. DDR3 PHY IP Matrix........................................................................................................ 54
Appendix A. LatticeECP3 DDR3 PHY IP Locate Constraints............................................................ 55
IPUG96_2.1, October 2016
4
DDR3 PHY IP Core User Guide
Chapter 1:
Introduction
The Double Data Rate (DDR3) Physical Interface (PHY) IP core is a general purpose IP core that provides connec-
tivity between a DDR3 Memory Controller (MC) and DDR3 memory devices compliant with JESD79-3 specifica-
tion. This DDR3 PHY IP core provides the industry standard DDR PHY Interface (DFI) bus at the local side to
interface with the memory controller. The DFI protocol defines the signals, signal relationships, and timing parame-
ters required to transfer control information and data to and from the DDDR3 devices over the DFI bus.
The DDR3 PHY IP core minimizes the effort required to integrate any available DDR3 memory controller with the
Lattice FPGA’s DDR3 primitives and thereby enables the user to implement only the logical portion of the memory
controller in the user design. The DDR3 PHY IP core contains all the logic required for memory device initialization,
write leveling, read data capture and read data de-skew that are dependent on Lattice FPGA DDR I/O primitives.
Quick Facts
Table 1-1 gives quick facts about the DDR3 SDRAM Controller IP core for ECP5
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