GS81302D06/11/20/38E-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
144Mb SigmaQuad-II+
Burst of 4 SRAM
500 MHz–350 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
m
en
The GS81302D06/11/20/38E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302D06/11/20/38E SigmaQuad SRAMs
m
-500
de
Parameter Synopsis
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
tKHKH
2.0 ns
0.45 ns
N
ot
Rev: 1.05c 8/2017
Re
co
tKHQV
d
SigmaQuad™ Family Overview
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 8 has a
4M addressable index).
1/31
fo
rN
ew
The GS81302D06/11/20/38E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
D
es
Clocking and Addressing Schemes
ig
© 2011, GSI Technology
n
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Analogue and Mixed Signal
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