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GS8662R08BD-250

Description
Static random access memory 1.8 or 1.5V 8M x 8 64M
Categorystorage    storage   
File Size359KB,35 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
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GS8662R08BD-250 Overview

Static random access memory 1.8 or 1.5V 8M x 8 64M

GS8662R08BD-250 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeBGA
package instructionLBGA, BGA165,11X15,40
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Factory Lead Time8 weeks
Maximum access time0.45 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)250 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density67108864 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals165
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5/1.8,1.8 V
Certification statusNot Qualified
Maximum seat height1.4 mm
Minimum standby current1.7 V
Maximum slew rate0.425 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width13 mm
GS8662R08/09/18/36BD-400/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36, x18 and x9) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
72Mb SigmaDDR-II
TM
Burst of 4 SRAM
400 MHz–250 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 and A1 are used to initialize the pointers that control
the data multiplexer / de-multiplexer so the RAM can perform
"critical word first" operations. From an external address point
of view, regardless of the starting point, the data transfers
always follow the same linear sequence {00, 01, 10, 11} or
{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where
the digits shown represent A1, A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B4 RAMs are two address pins less than the advertised index
depth (e.g., the 8M x 8 has a 2M addressable index, and A0 and
A1 are not accessible address pins).
SigmaDDR™ Family Overview
The GS8662R08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662R08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662R08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
Parameter Synopsis
-400
tKHKH
tKHQV
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.02d 8/2017
1/35
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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