GS8662S36BGD-300I datasheet, PDF

Datasheet> All Categories > storage> storage> GS8662S36BGD-300I

GS8662S36BGD-300I: DescriptionStatic random access memory 1.8 or 1.5V 2M x 36 72M; Categorystorage storage; File Size366KB，35 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric View All

GS8662S36BGD-300I Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	GS8662S36BGD-300I	-	-	View	Buy Now

GS8662S36BGD-300I Overview

Static random access memory 1.8 or 1.5V 2M x 36 72M

GS8662S36BGD-300I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	8 weeks
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	75497472 bit
Memory IC Type	STANDARD SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

Preview

Download Datasheet

View All

GS8662S08/09/18/36BD-400/350/333/300/250

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaSIO

DDR -II

Burst of 2 SRAM

Clocking and Addressing Schemes

400 MHz–250 MHz

1.8 V V

1.8 V and 1.5 V I/O

A Burst of 2SigmaSIO DDR-II SRAM is a synchronous

device. It employs dual input register clock inputs, K and K.

The device also allows the user to manipulate the output

K clocks are routed internally to fire the output registers

instead. Each Burst of 2SigmaSIO DDR-II SRAM also

supplies Echo Clock outputs, CQ and CQ, which are

synchronized with read data output. When used in a source

synchronous clocking scheme, the Echo Clock outputs can be

used to fire input registers at the data’s destination.

Each internal read and write operation in a SigmaSIO DDR-II

B2 RAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaSIO DDR-II B2 is always one address pin less

than the advertised index depth (e.g., the 8M x 8 has an 4M

addressable index).

SigmaSIO™ Family Overview

GS8662S08/09/18/36BD are built in compliance with the

SigmaSIO DDR-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Parameter Synopsis

-400

tKHKH

tKHQV

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

Rev: 1.02d 8/2017

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

High-voltage motor phase-to-phase short circuit and over-current protection circuit a

Countermeasures against external interference in general frequency converters (2)

3V battery cold end compensation thermocouple amplifier circuit

Anti-bounce circuit using TTL NAND gate

Current transformer circuit for measuring DC and AC currents

Absolutely usable switching power supply: Sanyo 83P power supply

VGA Display Circle - Simple Design and Application FPGA: [color=#000][font=Arial][size=14px][color=rgb(51, 51, 51)]1 Project Background Technical Exchange Group: 544453837, [/color][/size][/font][/color] [color=rgb(51, 51, 51)][font=Arial][size=17px][align=...; guyu_1 FPGA/CPLD

Can such hardware be networked smoothly?: The hardware corresponding to the z-stack protocol stack is 5 buttons and N LED lights, but the device I have only has one button and one LED light. Can such hardware realize the function? If so, how ...; peterjiejie RF/Wirelessly

I am a DSP novice. What should I pay attention to? How can I learn faster? I hope you can give me some suggestions. . . .: I have learned microcontrollers before... But I have never soldered a circuit board. Now I want to learn DSP to do motor control. I would like to ask all the DSP seniors what should I pay attention to...; zxya128 Embedded System

I'm an electronics idiot, and I want to make a VGA switcher, but I can't make it. Can I ask how I can modify it?: I don't know much about electronics, but I wanted to make a VGA switch. I used HCF4053 on a perf board to build a simple VGA switch, and it worked (the effect was very poor, with ghosting). So I thoug...; 默认密码 Integrated technical exchanges

SDR development board BladeRF, HackRF, USRP: If you have an SDR development board and need it for your project, you can buy it or rent it. The price is negotiable. Your contact information is QQ: 547409723. Please make a note when adding me. Tha...; 撒哈拉沙漠 RF/Wirelessly

I haven’t started buying C2000 yet, and now Sitara AM355x is here, so awesome!: Thank you to everyone at EEWorld for your hard work and TI for your support!...; wuyanyanke DSP and ARM Processors

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components