Ultralow Profile, 500 mA, 6 MHz, Synchronous,
Step-Down, DC-to-DC Converters
Data Sheet
FEATURES
1.20 V and 1.26 V fixed output voltage options
Clock signal enable
Logic signal enable also available on certain models
6 MHz operating frequency
Spread spectrum frequency modulation to reduce EMI
500 mA continuous output current
Input voltage: 2.1 V to 5.5 V
0.3 μA (typical) shutdown supply current
Pin-selectable power-saving mode
Compatible with tiny multilayer inductors
Internal synchronous rectifier
Internal compensation
Internal soft start
Output-to-ground short-circuit protection
Current-limit protection
Undervoltage lockout
Thermal shutdown protection
0.330 mm height (maximum), 6-ball BUMPED_CHIP (ADP2126)
0.200 mm height (maximum), 6-pad EWLP (ADP2127)
ADP2126/ADP2127
TYPICAL APPLICATIONS CIRCUIT
ADP2126/
ADP2127
A2
VIN
INPUT
VOLTAGE
2.1V TO 5.5V
C
IN
2.2µF
L
1.0µH
SW
B1
OUTPUT
VOLTAGE
1.20V OR 1.26V
C
OUT
2.2µF
C2
GND
FB
C1
MODE
A1
EXTCLK
B2
PWM
AUTO
OFF ON
OR
OFF
09658-001
ON
*
*LOGIC HIGH ENABLE IS ONLY AVAILABLE ON CERTAIN MODELS.
Figure 1.
APPLICATIONS
Mobile phones
Digital still/video cameras
Digital audio
Portable equipment
Camera modules
Image stabilization systems
GENERAL DESCRIPTION
The
ADP2126/ADP2127
are high frequency, step-down, dc-to-
dc converters optimized for portable applications in which board
area and battery life are critical constraints. The fixed 6 MHz
operating frequency enables the use of tiny ceramic inductors
and capacitors and the regulators use spread spectrum frequency
modulation to reduce EMI. Additionally, synchronous rectification
improves efficiency and results in fewer external components.
At high load currents, the ADP2126/ADP2127 use a voltage
regulating pulse-width modulation (PWM) mode that maintains
a constant frequency with excellent stability and transient response.
Light load operation is determined by the state of the MODE pin.
In forced PWM mode, the converter continues operating in PWM
for light loads. Under light load conditions in auto mode, the
ADP2126/ADP2127 automatically enter a power-saving mode,
which uses pulse frequency modulation (PFM) to reduce the
effective switching frequency, thus ensuring the longest battery
life in portable applications.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The ADP2126/ADP2127 are enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. Certain models
can also be enabled with a logic high signal. When the external clock
is not switching and in a low logic state, the ADP2126/ADP2127
stop regulating and shut down to draw less than 0.3 μA (typical)
from the source.
The ADP2126/ADP2127 have an input voltage range of 2.1 V to
5.5 V, allowing the use of single Li+/Li polymer cell, three-cell
alkaline, NiMH cell, and other standard power sources. The
ADP2126/ADP2127 are internally compensated to minimize
external components and can source up to 500 mA. Other key
features, such as cycle-by-cycle peak current limit, soft start,
undervoltage lockout (UVLO), output-to-ground short-circuit
protection, and thermal shutdown provide protection for internal
and external circuit components.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADP2126/ADP2127
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Overview...................................................................................... 11
Data Sheet
External Clock (EXTCLK) Enable ........................................... 11
Spread Spectrum Oscillator ...................................................... 12
Mode Selection ........................................................................... 12
Internal Control Features .......................................................... 12
Protection Features .................................................................... 13
Timing Constraints .................................................................... 13
Applications Information .............................................................. 14
Inductor Selection ...................................................................... 14
Input Capacitor Selection.......................................................... 14
Output Capacitor Selection....................................................... 15
Thermal Considerations............................................................ 15
PCB Layout Guidelines.................................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
3/12—Rev. A to Rev. B
Combined Figure 1 and Figure 2; Renumbered Sequentially..... 1
Changes to Undervoltage Lockout (UVLO) Section,
Added Figure 29, Renumbered Sequentially .............................. 13
Changes to Table 6.......................................................................... 14
Changes to Ordering Guide .......................................................... 18
5/11—Rev. 0 to Rev. A
Changes to Figure 35...................................................................... 17
5/11—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
SPECIFICATIONS
ADP2126/ADP2127
V
IN
= 3.6 V, T
A
= 25°C for typical specifications, and T
A
= T
J
= −40°C to +85°C for minimum and maximum specifications, unless
otherwise noted. All specifications at temperature extremes are guaranteed via correlation using the standard statistical quality control
(SQC) methods. Typical specifications are not guaranteed.
Table 1.
Parameter
SUPPLY
Operating Input Voltage Range
PWM Mode Quiescent Current
Auto Mode Quiescent Current
Shutdown Current
1
UNDERVOLTAGE LOCKOUT
Rising V
IN
Threshold
Falling V
IN
Threshold
OUTPUT
Continuous Output Current
2
PWM Mode Output Accuracy
3
PFM Mode Output Accuracy
3, 4
FB Bias Current
FB Pull-Down Resistance
SWITCHING CHARACTERISTICS
PMOS On Resistance
NMOS On Resistance
SW Leakage Current
PMOS Switch Current Limit
PFM Current Limit
Oscillator Frequency
SHORT-CIRCUIT PROTECTION
Rising V
OUT
Threshold
Falling V
OUT
Threshold
EXTCLK INPUT
High Threshold Voltage
Low Threshold Voltage
Leakage Current
Duty Cycle Operating Range
Frequency Operating Range
MODE INPUT LOGIC
High Threshold Voltage
Low Threshold Voltage
Leakage Current
THERMAL SHUTDOWN
5
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Symbol
V
IN
No load, V
MODE
= V
IN
No load, V
MODE
= 0 V, V
FB
> V
OUT
, SW = open
V
EXTCLK
= 0 V, open loop
Test Conditions/Comments
Min
2.1
12
300
0.3
1.9
1.8
Typ
Max
5.5
500
1.5
2.1
Unit
V
mA
μA
μA
V
V
1.5
I
LOAD
V
OUT
V
IN
= 2.1 V to 5.5 V
V
IN
= 2.1 V to 5.5 V, no load
V
IN
= 2.1 V to 5.5 V
V
FB
= V
OUT
V
EXTCLK
= 0 V, I
FB
= 10 mA
I
SW
= 500 mA
I
SW
= 500 mA
V
SW
= 0 V, V
IN
= 5.5 V
Open loop
V
MODE
= 0 V, V
IN
= 3.6 V
f
SW
500
V
OUT
− 2%
V
OUT
− 3%
R
DSCHG
4
110
180
250
770
170
4.8
1000
260
6
0.55
0.52
mA
V
OUT
+ 2% V
V
OUT
+ 3% V
9
μA
180
Ω
340
10
1291
305
6.8
0.7
mΩ
mΩ
μA
mA
mA
MHz
V
V
V
V
μA
%
MHz
V
V
μA
°C
°C
0.4
V
EXTCLK(H)
V
EXTCLK(L)
D
EXTCLK
f
EXTCLK
V
MODE(H)
V
MODE(L)
V
IN
= 2.1 V to 5.5 V
V
IN
= 2.1 V to 5.5 V
V
EXTCLK
= 0 V, V
IN
= V
MODE
= 5.5 V
PWM mode only
V
IN
= 2.1 V to 5.5 V
V
IN
= 2. 1 V to 5.5 V
V
IN
= 5.5 V, V
EXTCLK
= 2.1 V to 5.5 V
1.3
0.01
40
6
1.3
0.005
146
13
0.4
1
60
27
0.4
1
Rev. B | Page 3 of 20
ADP2126/ADP2127
Parameter
TIMING
VIN High to EXTCLK On
2
EXTCLK On to V
OUT
Rising
EXTCLK On to V
OUT
Rising
V
OUT
Power-Up Time (Soft Start)
2
EXTCLK Off to V
OUT
Falling
EXTCLK Off to V
OUT
Falling
V
OUT
Power-Down Time
Minimum Shutdown Time
2
Minimum Power-Off Time
2
1
2
Data Sheet
Symbol
t
1
t
2 (CLOCK)
t
2 (LOGIC)
t
3
t
5 (CLOCK)
t
5 (LOGIC)
t
6
t
5
+ t
6
t
7
Test Conditions/Comments
See Figure 2 and Figure 3
V
IN
= 2.1 V to 5.5 V
D
EXTCLK
= 40% to 60%, f
EXTCLK
= 6 MHz
D
EXTCLK
= 40% to 60%, f
EXTCLK
= 27 MHz
EXTCLK = logic high
C
OUT
= 2.2 μF, R
LOAD
= 3.6 Ω
D
EXTCLK
= 40% to 60%, f
EXTCLK
= 6 MHz to 27 MHz
EXTCLK = logic high, no load
C
OUT
= 2.2 μF, R
LOAD
= 3.6 Ω
C
OUT
= 2.2 μF, no load
C
OUT
= 2.2 μF, no load
Min
200
250
250
285
Typ
Max
Unit
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
320
320
315
70
9
0
16
465
400
400
385
200
17
1400
500
The total shutdown current is the addition of VIN shutdown current and SW leakage.
Guaranteed by design.
3
Transients not included in voltage accuracy specifications.
4
The PFM output voltage will be higher than the PWM output voltage. See the Typical Performance Characteristics section.
5
Thermal shutdown protection is only active in PWM mode.
TIMING DIAGRAMS
VIN
V
IN
× 90%
t
7
t
6
V
OUT(NOM)
× 10%
V
IN
× 10%
t
3
V
OUT
t
2
EXTCLK
t
5
09658-003
t
1
Figure 2. Clock Enable I/O Timing Diagram
VIN
V
IN
× 90%
t
7
t
6
V
OUT(NOM)
× 10%
V
IN
× 10%
t
3
V
OUT
t
2
EXTCLK
t
5
09658-004
t
1
Figure 3. Logic Enable I/O Timing Diagram (Logic High Enable Feature Available Only on Certain Models)
Rev. B | Page 4 of 20
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN to GND
EXTCLK to GND
SW, MODE to GND
FB to GND
Operating Ambient Temperature (T
A
)
Operating Junction Temperature (T
J
)
at I
LOAD
= 500 mA
Soldering Conditions
1
ADP2126/ADP2127
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits.
The operating junction temperature (T
J
) of the device is dependent
on the ambient temperature (T
A
), the power dissipation of the
device (P
D
), and the junction-to-ambient thermal resistance of
the package (θ
JA
). T
J
is calculated using the following formula:
T
J
=
T
A
+ (P
D
×
θ
JA
)
(1)
See the Applications Information section for further information
on calculating the operating junction temperature for a specific
application.
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +3.6 V
–40°C to +85°C
1
–40°C to +125°C
JEDEC J-STD-020
The maximum operating junction temperature (T
J (MAX)
) supersedes the
maximum operating ambient temperature (T
A (MAX)
). See the Thermal
Considerations section for more information.
THERMAL RESISTANCE
θ
JA
of the package is based on modeling and calculation using a
4-layer board. θ
JA
is highly dependent on the application and
board layout. In applications where high maximum power
dissipation exists, attention to thermal board design is required.
The value of θ
JA
may vary, depending on PCB material, layout,
and environmental conditions.
θ
JA
is specified for worst-case conditions, that is, a device soldered
on a circuit board for surface-mount packages. θ
JA
is determined
according to JEDEC Standard JESD51-9 on a 4-layer printed
circuit board (PCB).
Table
3
. Thermal Resistance (4-Layer PCB)
Package Type
6-Ball Bumped Bare Die Sales
6-Pad Embedded Wafer Level Package
θ
JA
105
105
Unit
°C/W
°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination.
THERMAL CONSIDERATIONS
The maximum operating junction temperature (T
J (MAX)
)
supersedes the maximum operating ambient temperature
(T
A (MAX)
) because the
ADP2126/ADP2127
may be damaged
when the junction temperature limits are exceeded. Monitoring
ambient temperature does not guarantee that T
J
is within the
specified temperature limits.
In applications with high power dissipation and poor PCB
thermal resistance, the maximum ambient temperature may
need to be derated. In applications with moderate power
dissipation and good PCB thermal resistance, the maximum
ESD CAUTION
Rev. B | Page 5 of 20
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