15-output DB1900Z Low-Power Derivative
9ZXL1550
DATASHEET
Description
The 9ZXL1550 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21501. It is
pin-compatible to the 9ZXL1530 and has the output
terminations integrated. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Features/Benefits
•
LP-HCSL outputs; up to 90% IO power reduction, better
•
•
•
•
•
•
•
•
•
•
•
signal integrity over long traces
Direct connect to 85Ω transmission lines; eliminates 60
termination resistors, saves 103mm
2
area
Pin compatible to the 9ZXL1530; easy upgrade to reduced
board space
64-VFQFPN package; smallest 15 output Z-buffer
Fixed feedback path: ~ 0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
100MHz & 133.33MHz PLL mode; legacy QPI/UPI support
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Key Specifications
•
•
•
•
•
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: <75ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
Output Features
•
15 - LP-HCSL Differential Output Pairs w/integrated
terminations (Zo = 85)
Block Diagram
FBOUT_NC
Z-PLL
(SS Compatible)
DIF_IN
DIF_IN#
DIF(14:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1550 REVISION E 11/20/15
1
©2015 Integrated Device Technology, Inc.
9ZXL1550 DATASHEET
Pin Configuration
DIF14#
DIF13#
DIF12#
DIF11#
DIF10#
VDDIO
VDDIO
DIF14
DIF13
DIF12
DIF11
DIF10
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DIF4
DIF4#
VDDIO
GND
VDDIO
GND
DIF9#
DIF9
DIF8#
DIF8
GND
VDD
DIF7#
DIF7
DIF6#
DIF6
VDDIO
GND
DIF5#
DIF5
GND
GND
GND
VDD
DIF2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA
GNDA
100M_133M#
HIBW_BYPM_LOBW#
CKPWRGD_PD#
GND
VDDR
DIF_IN
DIF_IN#
SMB_A0_tri
SMBDAT
SMBCLK
SMB_A1_tri
FBOUT_NC#
FBOUT_NC
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIF0
DIF0#
VDDIO
GND
9ZXL1550
EPAD is Pin 65
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DIF1
DIF1#
DIF2#
GND
VDD
DIF3
DIF3#
9x9 mm 64-pin VFQFPN
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Power Management Table
Inputs
CKPWRGD_PD#
0
1
DIF_IN/
DIF_IN#
X
Running
Outputs
Control Bits
SMBus
DIFx/
FBOUT_NC/
EN bit
DIFx#
FBOUT_NC#
X
Low/Low
Low/Low
0
Low/Low
Running
1
Running
Running
PLL State
OFF
ON
ON
Power Connections
GND
2
6
16,20,25,32,
19,31,36,48,5
26, 41, 58
35,42,47,52,
1,63
57,64
VDD
1
7
Pin Number
VDDIO
Description
Analog PLL
Analog Input
DIF clocks
PLL Operating Mode
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
Tri-Level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
(MHz)
100.00
133.33
DIFx
(MHz)
DIF_IN
DIF_IN
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
2
REVISION E 11/20/15
9ZXL1550 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 VDDA
2 GNDA
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TYPE
DESCRIPTION
PWR Power for the PLL core.
GND Ground pin for the PLL core.
3.3V Input to select operating frequency.
100M_133M#
IN
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
HIBW_BYPM_LOBW#
IN
See PLL Operating Mode Table for Details.
3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down
CKPWRGD_PD#
IN
Mode on subsequent assertions. Low enters Power Down Mode.
GND
GND Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
VDDR
PWR
filtered appropriately.
DIF_IN
IN
HCSL True input
DIF_IN#
IN
HCSL Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
SMB_A0_tri
IN
SMBus Addresses.
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
SMB_A1_tri
IN
SMBus Addresses.
Complementary half of differential feedback output. This pin should NOT be connected to anything outside
FBOUT_NC#
OUT
the chip. It exists to provide delay path matching to get 0 propagation delay.
True half of differential feedback output. This pin should NOT be connected to anything outside the chip.
FBOUT_NC
OUT
It exists to provide delay path matching to get 0 propagation delay.
GND
GND Ground pin.
DIF0
OUT Differential true clock output
DIF0#
OUT Differential Complementary clock output
VDDIO
PWR Power supply for differential outputs
GND
GND Ground pin.
DIF1
OUT Differential true clock output
DIF1#
OUT Differential Complementary clock output
DIF2
OUT Differential true clock output
DIF2#
OUT Differential Complementary clock output
GND
GND Ground pin.
VDD
PWR Power supply, nominal 3.3V
DIF3
OUT Differential true clock output
DIF3#
OUT Differential Complementary clock output
DIF4
OUT Differential true clock output
DIF4#
OUT Differential Complementary clock output
VDDIO
PWR Power supply for differential outputs
GND
GND Ground pin.
REVISION E 11/20/15
3
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
9ZXL1550 DATASHEET
Pin Descriptions (cont.)
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
PIN NAME
DIF5
DIF5#
GND
VDDIO
DIF6
DIF6#
DIF7
DIF7#
VDD
GND
DIF8
DIF8#
DIF9
DIF9#
GND
VDDIO
DIF10
DIF10#
VDDIO
GND
DIF11
DIF11#
DIF12
DIF12#
GND
VDD
DIF13
DIF13#
DIF14
DIF14#
VDDIO
GND
EPAD
TYPE
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
GND
DESCRIPTION
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Epad should be connected to GND
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
4
REVISION E 11/20/15
9ZXL1550 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZXL1550. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
I/O Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA, R
VDD
VDDIO
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
4.6
V
DD
+0.5V
5.5V
UNITS NOTES
V
V
V
V
V
V
C
°C
V
°
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
1,2
1,2
1,2
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics–DIF_IN Clock Input Parameters
TA = T
COM
; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
Input Crossover Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
CROSS
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Cross Over Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
150
300
0.4
-5
45
0
TYP
MAX
900
UNITS NOTES
mV
mV
1
1
1,2
1
1
8
5
55
125
V/ns
uA
%
ps
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
REVISION E 11/20/15
5
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
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