GS840Z18CGT/GS840Z36CGT
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• 256K x 18 and 128K x 36 configurations
• User configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• Pin-compatible with 2Mb, 9Mb and 18Mb devices
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered address, data, and control
• ZZ Pin for automatic power-down
• RoHS-compliant 100-lead TQFP package
4Mb Pipelined and Flow Through
Synchronous NBT SRAMs
250 MHz–100 MHz
3.3 V V
DD
2.5 V and 3.3 V V
DDQ
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS840Z18/36CGT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS840Z18/36CGT is implemented with GSI's high
performance CMOS technology and is available in a 6/6
RoHS-compliant, JEDEC-standard 100-pin TQFP package.
Functional Description
The GS840Z18/36CGT is a 4Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
tCycle
t
KQ
I
DD
t
KQ
tCycle
I
DD
–250
4.0 ns
2.5 ns
TBD
5.5 ns
5.5 ns
TBD
–200
5.5 ns
3.0 ns
TBD
6.5 ns
6.5 ns
TBD
–166
6.0 ns
3.5 ns
TBD
7.0 ns
7.0 ns
TBD
–150
6.7 ns
3.8 ns
TBD
7.5 ns
7.5 ns
TBD
–100
10 ns
4.5 ns
TBD
12 ns
12 ns
TBD
Rev: 1.01 8/2011
1/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840Z18CGT/GS840Z36CGT
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
DQ
A
DQ
B
DQ
C
DQ
D
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
I/O
I/O
In
In
In
In
In
In
—
Description
Burst Address Inputs; preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active high; for self decoded depth expansion
Chip Enable; active low, for self decoded depth expansion
Output Enable; active low
Advance / Load—Burst address counter control pin
Clock Input Buffer Enable; active low
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
3.3 V power supply
Ground
3.3 V output power supply for noise reduction
No Connect
Rev: 1.01 8/2011
4/22
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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