GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D)
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
400 MHz–150 MHz
1.8 V, 2.5 V, or 3.3 V V
DD
1.8 V, 2.5 V, or 3.3 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V, 2.5 V, or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and
144Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 165-bump BGA package
• RoHS-compliant 100-pin TQFP and 165-bump BGA
packages available
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18D(GT/D)/GS8161Z32D(D)/
GS8161Z36D(GT/D) may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, in addition to the rising-edge-triggered
registers that capture input signals, the device incorporates a
rising-edge-triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge triggered
output register during the access cycle and then released to the
output drivers at the next rising edge of clock.
The GS8161Z18D(GT/D)/GS8161Z32D(D)/
GS8161Z36D(GT/D) is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 165-bump BGA package.
Functional Description
The GS8161Z18D(GT/D)/GS8161Z32D(D)/
GS8161Z36D(GT/D) is an 18Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-400
2.5
2.5
370
430
4.0
4.0
275
315
-375
2.5
2.66
350
410
4.2
4.2
265
300
-333
2.5
3.3
310
365
4.5
4.5
255
285
-250
2.5
4.0
250
290
5.5
5.5
220
250
-200
3.0
5.0
210
240
6.5
6.5
205
225
-150
3.8
6.7
185
200
7.5
7.5
190
205
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.03b 9/2013
1/40
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18D(GT/D)/GS8161Z32D(D)/GS8161Z36D(GT/D)
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A,
DQP
A
DQ
B,
DQP
B
DQ
C,
DQP
C
DQ
D,
DQP
D
ZZ
FT
LBO
MCH
TMS
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
In
In
In
—
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
Must Connect High (165 BGA only)
Scan Test Mode Select
Rev: 1.03b 9/2013
4/40
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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