GS82582D18/36GE-400/375/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 144 Mb devices
• RoHS-compliant 165-bump BGA package
288Mb SigmaQuad-II
TM
Burst of 4 SRAM
Clocking and Addressing Schemes
400 MHz–250 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
The GS82582D18/36GE SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaQuad-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 18 has an
4M addressable index).
SigmaQuad™ Family Overview
The GS82582D18/36GE are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582D18/36GE SigmaQuad SRAMs are just
one element in a family of low power, low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
Parameter Synopsis
-400
tKHKH
tKHQV
2.5 ns
0.45 ns
-375
2.66 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.04 4/2016
1/30
© 2012, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82582D18/36GE-400/375/333/300/250
Pin Description Table
Symbol
SA
R
W
BW0–BW3
K
K
C
C
TMS
TDI
TCK
TDO
V
REF
ZQ
Qn
Dn
Description
Synchronous Address Inputs
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Input Clock
Input Clock
Output Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Synchronous Data Outputs
Synchronous Data Inputs
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
No Connect
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Output
Output
Supply
Supply
Supply
—
Comments
—
Active Low
Active Low
Active Low
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
—
Active Low
—
—
1.8 V Nominal
1.5 or 1.8 V Nominal
—
—
D
off
CQ
CQ
V
DD
V
DDQ
V
SS
NC
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to V
DDQ
, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. C, C, K, K cannot be set to V
REF
voltage.
Rev: 1.04 4/2016
4/30
© 2012, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82582D18/36GE-400/375/333/300/250
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read
port deselect cycle.
Read A
NOP
Read B
Write C
Read D
Write E
NOP
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
A
A+1
A+2
A+3
B
B+1
B+2
B+3
D
D+1
D+2
C
C
C+1
C+1
C+2
C+2
C+3
C+3
E
E
E+1
E+1
A
B
C
D
E
Rev: 1.04 4/2016
5/30
© 2012, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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