GS8342Q18BD-250I datasheet, PDF

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GS8342Q18BD-250I: DescriptionStatic random access memory 1.8 or 1.5V 2M x 18 36M; Categorystorage storage; File Size453KB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8342Q18BD-250I Overview

Static random access memory 1.8 or 1.5V 2M x 18 36M

GS8342Q18BD-250I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	10 weeks 3 days
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	37748736 bit
Memory IC Type	QDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.215 A
Minimum standby current	1.7 V
Maximum slew rate	0.675 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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GS8342Q08/09/18/36BD-357/333/300/250

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 144 Mb devices

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

36Mb SigmaQuad-II

Burst of 2 SRAM

Clocking and Addressing Schemes

357 MHz–250 MHz

1.8 V V

1.8 V and 1.5 V I/O

The GS8342Q08/09/18/36BD SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Each internal read and write operation in a SigmaQuad-II B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II B2 RAM is always one address pin less than the

advertised index depth (e.g., the 4M x 8 has an 2M addressable

index).

SigmaQuad™ Family Overview

The GS8342Q08/09/18/36BD are built in compliance with the

SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 37,748,736-bit (36Mb)

SRAMs. The GS8342Q08/09/18/36BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Parameter Synopsis

-357

tKHKH

tKHQV

2.8 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

Rev: 1.02c 8/2017

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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