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GS8662D06BGD-500

Description
Static random access memory 1.8 or 1.5V 8M x 8 64M
Categorystorage    storage   
File Size338KB,33 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
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GS8662D06BGD-500 Overview

Static random access memory 1.8 or 1.5V 8M x 8 64M

GS8662D06BGD-500 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerGSI Technology
Parts packaging codeBGA
package instructionLBGA,
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Factory Lead Time8 weeks
Maximum access time0.45 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PBGA-B165
length15 mm
memory density67108864 bit
Memory IC TypeQDR SRAM
memory width8
Number of functions1
Number of terminals165
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8MX8
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width13 mm
GS8662D20/38BD-550/500/450/400/350
GS8662D06/11BD-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
72Mb SigmaQuad-II+
TM
Burst of 4 SRAM
550 MHz–350 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
SRAMs. The GS8662D06/11/20/38BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662D06/11/20/38BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 8M x 8 has a 2M
addressable index).
SigmaQuad-II™ Family Overview
The GS8662D06/11/20/38BD are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
Parameter Synopsis (x18/x36)
-550
tKHKH
tKHQV
1.81 ns
0.29ns
-500
2.0 ns
0.33 ns
-450
2.2 ns
0.37 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Parameter Synopsis (x8/x9)
-500
tKHKH
tKHQV
2.0 ns
0.33 ns
-450
2.2 ns
0.37ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.02c 8/2017
1/33
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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