128M DDR1 -AS4C8M16D1
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Fast clock rate: 250/200MHz
•
Operating temperature:
- Commercial (0°C~70
°
C)
- Industrial (-40°C~85
°
C)
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Differential Clock CK &
CK
input
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Bi-directional DQS
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DLL enable/disable by EMRS
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Fully synchronous operation
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Internal pipeline architecture
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Four internal banks, 2M x 16-bit for each bank
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Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
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Individual byte write mask control
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DM Write Latency = 0
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Auto Refresh and Self Refresh
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4096 refresh cycles / 64ms
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Precharge & active power down
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Power supplies: VDD & VDDQ = 2.5V
±
0.2V
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Interface: SSTL_2 I/O Interface
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Package: 60-Ball, 8x13x1.2 mm (max) FBGA
- Pb free and Halogen free
128M DDR1 -AS4C8M16D1
The 128Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits.
It is internally configured as a quad 2M x 16 DRAM with a synchronous interface (all signals are registered
on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the
registration of a BankActivate command which is then followed by a Read or Write command. The device
provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In addition, 128Mb DDR features programmable DLL
option. By having a programmable mode register and extended mode register, the system can choose the
most suitable modes to maximize its performance. These devices are well suited for applications requiring
high memory bandwidth and high performance.