GS8662QT10BGD-250I datasheet, PDF

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GS8662QT10BGD-250I: DescriptionStatic random access memory 1.8 or 1.5V 8M x 9 72M; Categorystorage storage; File Size317KB，28 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8662QT10BGD-250I Overview

Static random access memory 1.8 or 1.5V 8M x 9 72M

GS8662QT10BGD-250I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	8 weeks
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	75497472 bit
Memory IC Type	QDR SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX9
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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GS8662QT07/10/19/37BD-357/333/300/250/200

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad-II+

Burst of 2 SRAM

357 MHz–200 MHz

1.8 V V

1.8 V and 1.5 V I/O

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662QT07/10/19/37BD SigmaQuad-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaQuad-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaQuad-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 8 has an 4M

addressable index).

SigmaQuad™ Family Overview

The GS8662QT07/10/19/37BD are built in compliance with

the SigmaQuad-II+ SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662QT07/10/19/37BD SigmaQuad SRAMs

Parameter Synopsis

-357

tKHKH

tKHQV

2.8 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

Rev: 1.00b 8/2017

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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