TC58BYG1S3HBAI6
MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2 GBIT (256M
×
8 BIT) CMOS NAND E
2
PROM
DESCRIPTION
The TC58BYG1S3HBAI6 is a single 1.8V 2Gbit (2,214,592,512 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E
2
PROM) organized as (2048
+
64) bytes
×
64 pages
×
2048 blocks.
The device has a 2112-byte static register which allows program and read data to be transferred between the register
and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block unit
(128 Kbytes
+
4 Kbytes: 2112 bytes
×
64 pages).
The TC58BYG1S3HBAI6 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TC58BYG1S3HBAI6 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
x8
2112
×
128K
×
8
2112
×
8
2112 bytes
(128K
+
4K) bytes
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
•
•
•
Power supply
V
CC
=
1.7V to 1.95V
•
Access time
Cell array to register 40
µs
typ. (Single Page Read) / 55
µs
typ. (Multi Page Read)
25 ns min (C
L
=30pF)
Read Cycle Time
Program/Erase time
Auto Page Program
Auto Block Erase
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
330
µs/page
typ.
3.5 ms/block typ.
30 mA max
30 mA max
30 mA max
50
µA
max
•
•
•
Package
P-VFBGA67-0608-0.80-001 (Weight: 0.095 g typ.)
8bit ECC for each 528Byte is implemented on the chip.
•
© 2012-2018 Toshiba Memory Corporation
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2018-06-01C
TC58BYG1S3HBAI6
VALID BLOCKS
SYMBOL
N
VB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
2008
TYP.
MAX
2048
UNIT
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
V
CC
Power Supply Voltage
PARAMETER
MIN
1.7
TYP.
MAX
1.95
UNIT
V
V
IH
V
IL
*
High Level Input Voltage
Low Level Input Voltage
V
CC
x 0.8
−0.3*
V
CC
+
0.3
V
CC
x 0.2
V
V
−2
V (pulse width lower than 20 ns)
DC CHARACTERISTICS
(Ta
=
-40 to 85°C, V
CC
=
1.7 to 1.95V)
SYMBOL
I
IL
I
LO
I
CCO1
I
CCO2
I
CCO3
I
CCS
V
OH
V
OL
I
OL
(
RY / BY
)
PARAMETER
Input Leakage Current
Output Leakage Current
Serial Read Current
Programming Current
Erasing Current
Standby Current
High Level Output Voltage
Low Level Output Voltage
CONDITION
V
IN
=
0 V to V
CC
V
OUT
=
0 V to V
CC
CE
=
V
IL
, I
OUT
=
0 mA, t
RC
=
25 ns
MIN
V
CC
– 0.2
TYP.
4
MAX
±10
±10
30
30
30
50
0.2
UNIT
µA
µA
mA
mA
mA
µA
V
V
mA
CE
=
V
CC
−
0.2 V,
WP
=
0 V/V
CC
I
OH
= −0.1
mA
I
OL
=
0.1 mA
Output Current of
RY / BY
pin V
OL
=
0.2 V
© 2012-2018 Toshiba Memory Corporation
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2018-06-01C
TC58BYG1S3HBAI6
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
=
-40 to 85°C, V
CC
=
1.7 to 1.95V)
SYMBOL
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
WC
t
WH
t
WW
t
RR
t
RW
t
RP
t
RC
t
REA
t
CEA
t
CLR
t
AR
t
RHOH
t
RLOH
t
RHZ
t
CHZ
t
CSD
t
REH
t
IR
t
RHW
t
WHC
t
WHR
t
WB
t
RST
CLE Setup Time
CLE Hold Time
CE
Setup Time
CE
Hold Time
PARAMETER
MIN
12
5
20
5
12
12
5
12
5
25
10
100
20
20
12
25
10
10
25
5
0
10
0
30
30
60
MAX
20
25
60
20
100
5/5/10/500
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE
High Hold Time
WP
High to
WE
Low
Ready to
RE
Falling Edge
Ready to
WE
Falling Edge
Read Pulse Width
Read Cycle Time
RE
Access Time
CE
Access Time
CLE Low to
RE
Low
ALE Low to
RE
Low
RE
High to Output Hold Time
RE
Low to Output Hold Time
RE
High to Output High Impedance
CE
High to Output High Impedance
CE
High to ALE or CLE Don’t Care
RE
High Hold Time
Output-High-Impedance-to-
RE
Falling Edge
RE
High to
WE
Low
WE
High to
CE
Low
WE
High to
RE
Low
WE
High to Busy
Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP.
*2: tCS should be longer than tWP + 8ns.
© 2012-2018 Toshiba Memory Corporation
5
2018-06-01C
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