Dual Input Network Clock
Generator/Synchronizer
AD9549
FEATURES
Flexible reference inputs
Input frequencies: 8 kHz to 750 MHz
Two reference inputs
Loss of reference indicators
Auto and manual holdover modes
Auto and manual switchover modes
Smooth A-to-B phase transition on outputs
Excellent stability in holdover mode
Programmable 16 + 1-bit input divider, R
Differential HSTL clock output
Output frequencies to 750 MHz
Low jitter clock doubler for frequencies of >400 MHz
Single-ended CMOS output for frequencies of <150 MHz
Programmable digital loop filter (<1 Hz to ~100 kHz)
High speed digitally controlled oscillator (DCO) core
Direct digital synthesizer (DDS) with integrated 14-bit DAC
Excellent dynamic performance
Programmable 16 + 1-bit feedback divider, S
Software controlled power-down
Available 64-lead LFCSP package
APPLICATIONS
Network synchronization
Reference clock jitter cleanup
SONET/SDH clocks up to OC-192, including FEC
Stratum 3/3E reference clocks
Wireless base station, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9549 generates an output clock, synchronized to one of two
external input references. The external references may contain
significant time jitter, also specified as phase noise. Using a
digitally controlled loop and holdover circuitry, the AD9549
continues to generate a clean (low jitter), valid output clock during
a loss of reference condition, even when both references have failed.
The AD9549 operates over an industrial temperature range of
−40°C to +85°C.
BASIC BLOCK DIAGRAM
AD9549
FDBK_IN
S1 TO S4
DAC_OUT
FILTER
REFA_IN
REFB_IN
REFERENCE
MONITORS
AND
SWITCHING
R
DIGITAL PLL
R, S DIVIDERS
HOLDOVER
CLOCK
OUTPUT
DRIVERS
OUT
OUT_CMOS
SERIAL PORT,
I/O LOGIC
SYSTEM CLOCK
MULTIPLIER
06744-001
DIGITAL INTERFACE
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD9549
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Basic Block Diagram ........................................................................ 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 6
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 13
Input/Output Termination Recommendations .......................... 16
Theory of Operation ...................................................................... 17
Overview...................................................................................... 17
Digital PLL Core (DPLLC)........................................................ 17
Phase Detector ............................................................................ 21
Digital Loop Filter Coefficients ................................................ 22
Closed-Loop Phase Offset ......................................................... 24
Lock Detection ............................................................................ 24
Reference Monitors .................................................................... 26
Reference Switchover ................................................................. 27
Holdover ...................................................................................... 29
Output Frequency Range Control ............................................ 32
Reconstruction Filter ................................................................. 32
FDBK_IN Inputs ........................................................................ 33
Reference Inputs ......................................................................... 33
SYSCLK Inputs ........................................................................... 33
Harmonic Spur Reduction ........................................................ 35
Output Clock Drivers and 2× Frequency Multiplier ............. 36
Frequency Slew Limiter ............................................................. 37
Frequency Estimator .................................................................. 37
Status and Warnings ................................................................... 39
Thermal Performance .................................................................... 41
Power-Up ......................................................................................... 42
Power-On Reset .......................................................................... 42
Programming Sequence ............................................................ 42
Power Supply Partitioning............................................................. 43
3.3 V Supplies.............................................................................. 43
1.8 V Supplies.............................................................................. 43
Serial Control Port ......................................................................... 44
Serial Control Port Pin Descriptions ....................................... 44
Operation of Serial Control Port .............................................. 44
The Instruction Word (16 Bits) ................................................ 45
MSB/LSB First Transfers ........................................................... 45
I/O Register Map ............................................................................ 48
I/O Register Descriptions .............................................................. 53
Serial Port Configuration (Register 0x0000 to Register
0x0005) ........................................................................................ 53
Power-Down and Reset (Register 0x0010 to Register 0x0013)
....................................................................................................... 53
System Clock (Register 0x0020 to Register 0x0023) ............. 54
Digital PLL Control and Dividers (Register 0x0100 to
Register 0x0130) ......................................................................... 55
Free-Run (Single-Tone) Mode (Register 0x01A0 to Register
0x01AD) ...................................................................................... 61
Reference Selector/Holdover (Register 0x01C0 to Register
0x01C3)........................................................................................ 62
Doubler and Output Drivers (Register 0x0200 to Register
0x0201) ........................................................................................ 63
Monitor (Register 0x0300 to Register 0x0335)....................... 64
Calibration (User-Accessible Trim) (Register 0x0400 to
Register 0x0410) ......................................................................... 70
Harmonic Spur Reduction (Register 0x0500 to Register
0x0509) ........................................................................................ 71
Applications Information .............................................................. 73
Sample Applications Circuit ..................................................... 73
Outline Dimensions ....................................................................... 74
Ordering Guide .......................................................................... 74
Rev. D | Page 2 of 76
AD9549
REVISION HISTORY
12/10—Rev. C to Rev. D
Changes to I
AVDD
(Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30,
Pin44, Pin 45) Parameter ................................................................. 4
Changes to Total Power Dissipation Parameter and Added
Endnote 4 ........................................................................................... 5
Changes to Pin 59 Description ......................................................11
Changes to Direct Digital Synthesizer (DDS) Section ...............20
Changes to Power-Up Section .......................................................42
Changes to Address 0x0002 Default Value (in Table 13) ...........48
Changes to Address 0x0400 and Address 0x40E Default Values
(in Table 13) .....................................................................................52
5/10—Rev. B to Rev. C
Deleted 64-Lead LFCSP (CP-64-1) .................................. Universal
Changes to SYSCLK PLL Enabled/Minimum Differential Input
Level Parameter, Table 2 ................................................................... 6
Updated Outline Dimensions ........................................................74
Changes to Ordering Guide ...........................................................74
1/10—Rev. A to Rev. B
Changes to I/O Register Map Section, Introduction and
Table 13 .............................................................................................48
Changes to Register 0x0405 to Register 0x0408—Reserved
Section ..............................................................................................70
Added Register 0x0406—Part Version Section ...........................71
12/09—Rev. 0 to Rev. A
Added 64-Lead LFCSP (CP-64-7) ................................... Universal
Changes to Total Power Dissipation Parameter ............................ 5
Changes to Serial Port Timing Specifications and
Propagation Delay Parameters ........................................................ 8
Added Exposed Paddle Notation to Figure 2; Changes to
Table 4 ............................................................................................... 10
Corrected DDS Phase Offset Resolution from 16 Bits to
14 Bits Throughout; Change to Figure 25 .................................... 20
Changes to Phase Lock Detection Section .................................. 24
Change to Figure 30 ........................................................................ 25
Changes to Loss of Reference and Reference Frequency
Monitor Sections ............................................................................. 26
Change to Output Frequency Range Control Section ............... 32
Change to Figure 46 ........................................................................ 36
Changes to Frequency Estimator Section .................................... 37
Changes to Programming Sequence Section .............................. 42
Changes to Power Supply Partitioning Section........................... 43
Change to Serial Control Port Section ......................................... 44
Changes to Figure 54 ...................................................................... 46
Added Exposed Paddle Notation to Outline Dimensions and
Changes to Ordering Guide ........................................................... 74
8/07—Revision 0: Initial Version
Rev. D | Page 3 of 76
AD9549
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted.
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O (Pin 1)
DVDD (Pin 3, Pin 5, Pin 7)
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49)
AVDD3 (Pin 37)
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT
I
AVDD3
(Pin 14)
I
AVDD3
(Pin 37)
I
AVDD3
(Pin 46, Pin 47, Pin 49)
I
AVDD
(Pin 36, Pin 42)
I
AVDD
(Pin 11)
I
AVDD
(Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 44, Pin 45)
I
AVDD
(Pin 53)
I
DVDD
(Pin 3, Pin 5, Pin 7)
I
DVDD_I/O
(Pin 1)
LOGIC INPUTS (Except Pin 32)
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Input Current (I
INH
, I
INL
)
Maximum Input Capacitance (C
IN
)
CLKMODESEL (Pin 32) LOGIC INPUT
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Input Current (I
INH
, I
INL
)
Maximum Input Capacitance (C
IN
)
LOGIC OUTPUTS
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
REFERENCE INPUTS
Input Capacitance
Input Resistance
Differential Operation
Common Mode Input Voltage
1
(Applicable When DC-Coupled)
Differential Input Voltage Swing
1
Single-Ended Operation
Input Voltage High (V
IH
)
Input Voltage Low (V
IL
)
Threshold Voltage
Input Current
FDBK_IN INPUT
Input Capacitance
Input Resistance
Differential Input Voltage Swing
2
Min
3.135
1.71
3.135
1.71
1.71
Typ
3.30
1.80
3.30
3.30
1.80
Max
3.465
1.89
3.465
3.465
1.89
Unit
V
V
V
V
V
Test Conditions/Comments
Pin 37 is typically 3.3 V, but can be set to 1.8 V
4.7
3.8
26
21
12
215
41
254
4
2.0
DVSS
±60
3
1.4
AVSS
−18
3
5.6
4.5
29
26
15
281
49
265
6
DVDD_I/O
0.8
±200
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
µA
pF
V
V
µA
pF
REFA, REFB buffers
CMOS output clock driver at 3.3 V
DAC output current source, f
S
= 1 GSPS
FDBK_IN input, HSTL output clock driver
(output doubler turned on)
REFA and REFB input buffer 1.8 V supply
Aggregate analog supply, including system
clock PLL
DAC power supply
Digital core
Digital I/O (varies dynamically)
Pin 9, Pin 10, Pin 54 to Pin 61, Pin 63, Pin 64
At V
IN
= 0 V and V
IN
= DVDD_I/O
Pin 32 only
AVDD
0.4
−50
At V
IN
= 0 V and V
IN
= AVDD
Pin 62 and the following bidirectional pins:
Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
I
OH
= 1 mA
I
OL
= 1 mA
Pin 12, Pin 13, Pin 15, Pin 16
Differential at Register 0x040F[1:0] = 00
Differential operation; note that LVDS signals
must be ac-coupled
Differential operation
Register 0x040F[1:0] = 10
2.7
DVSS
3
11.5
DVDD_I/O
0.4
V
V
pF
kΩ
V
mV p-p
8.5
1.5
500
2.0
AVSS
AVDD3 −
0.66
14.5
AVDD3 −
0.2
AVDD3 −
0.82
AVDD3
0.8
AVDD3 −
0.98
1
V
V
V
mA
pF
kΩ
mV p-p
Register 0x040F[1:0] = 10 (other settings
possible)
Single-ended operation
Pin 40, Pin 41
Differential
−12 dBm into 50 Ω; must be ac-coupled
18
225
3
22
26
Rev. D | Page 4 of 76
AD9549
Parameter
SYSTEM CLOCK INPUT
SYSCLK PLL Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage
2
Differential Input Voltage Swing
3
SYSCLK PLL Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias Voltage
2
Differential Input Voltage Swing
3
Crystal Resonator with SYSCLK PLL Enabled
Motional Resistance
CLOCK OUTPUT DRIVERS
HSTL Output Driver
Differential Output Voltage Swing
Common-Mode Output Voltage
2
CMOS Output Driver
Output Voltage High (V
OH
)
Output Voltage Low (V
OL
)
Output Voltage High (V
OH
)
Output Voltage Low (V
OL
)
TOTAL POWER DISSIPATION
All Blocks Running
4
Power-Down Mode
Digital Power-Down Mode
Default with SYSCLK PLL Enabled
Default with SYSCLK PLL Disabled
With REFA or REFB Power-Down
With HSTL Clock Driver Power-Down
With CMOS Clock Driver Power-Down
Must be
≤0
V relative to AVDD3 (Pin 14) and
≥0
V relative to AVSS (Pin 33, Pin 43).
Relative to AVSS (Pin 33, Pin 43).
3
Must be
≤0
V relative to AVDD (Pin 36) and ≥0 V relative to AVSS (Pin 33, Pin 43).
4
Typical measurement done with only REFA and HSTL output doubler turned off.
1
2
Min
Typ
Max
Unit
Test Conditions/Comments
System clock inputs should always be ac-
coupled (both single-ended and differential)
Single-ended, each pin
Differential
0 dBm into 50 Ω
Single-ended, each pin
Differential
0 dBm into 50 Ω
25 MHz, 3.2 mm × 2.5 mm AT cut
2.4
0.93
632
1.5
2.6
1.17
2.8
1.38
pF
kΩ
V
mV p-p
pF
kΩ
V
mV p-p
Ω
2.4
0.93
632
3
2.6
1.17
2.8
1.38
9
100
1080
0.7
1280
0.88
1480
1.06
mV
V
Output driver static; see
Figure 12
for output
swing vs. frequency
Output driver static; see
Figure 13
and
Figure 14
for output swing vs. frequency
2.7
0.4
1.4
0.4
1060
24
565
955
945
1310
70
713
V
V
V
V
mW
mW
mW
mW
mW
mW
mW
mW
I
OH
= 1 mA, (Pin 37) = 3.3 V
I
OL
= 1 mA, (Pin 37) = 3.3 V
I
OH
= 1 mA, (Pin 37) = 1.8 V
I
OL
= 1 mA, (Pin 37) = 1.8 V
Worst case over supply, temperature, process
Using either the power-down and enable
register (Register 0x0010) or the PWRDOWN pin
After reset or power-up with f
S
= 1 GHz,
S4 = 0, S1 to S3 = 1, f
SYSCLK
= 25 MHz
After reset or power-up with f
S
= 1 GHz,
S1 to S4 = 1
One reference still powered up
1115
1105
1095
1107
Rev. D | Page 5 of 76
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