IS62WVS2568GBLL-45NLI-TR datasheet, PDF

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IS62WVS2568GBLL-45NLI-TR: DescriptionStatic random access memory 2Mb 256Kx8 45MHz 2.2-3.6V Serial static random access memory; Categorysemiconductor Memory IC Static random access memory; File Size810KB，26 Pages; ManufacturerISSI(Integrated Silicon Solution Inc.); Websitehttp://www.issi.com/; Environmental Compliance

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IS62WVS2568GBLL-45NLI-TR Overview

Static random access memory 2Mb 256Kx8 45MHz 2.2-3.6V Serial static random access memory

IS62WVS2568GBLL-45NLI-TR Parametric

Parameter Name	Attribute value
Maker	ISSI(Integrated Silicon Solution Inc.)
Product Category	static random access memory
storage	2 Mbit
organize	256 k x 8
maximum clock frequency	45 MHz
Interface Type	Serial
Supply voltage - max.	3.6 V
Supply voltage - min.	2.2 V
Supply current—max.	10 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
Installation style	SMD/SMT
Package/box	SOIC-8
Encapsulation	Cut Tape
Encapsulation	MouseReel
Encapsulation	Reel
series	IS62WVS2568GBLL
type	Fast Serial SRAM
Factory packaging quantity	3000

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IS62/65WVS2568GALL

IS62/65WVS2568GBLL

256Kx8 LOW VOLTAGE, FAST SERIAL SRAM

with SPI, SDI and SQI INTERFACE

KEY FEATURES

•

SPI-Compatible Bus Interface:

30/45 MHz Clock rate

SPI/SDI/SQI mode

•

Single Power Supply:

= 1.65V - 2.2V (IS62/65WVS2568GALL)

= 2.70V - 3.6V (IS62/65WVS2568GBLL)

•

Read Latency:

SPI mode: 8 clocks

DPI mode: 4 clocks

QPI mode: 2 clocks

•

Low-Power CMOS Technology:

Read Current: 10 mA(max) at 3.6V, 45 MHz, 85°C

CMOS Standby Current: 4

A(typ)

•

512K x 8-bit Organization:

32-byte page

•

Byte, Page and Sequential mode for Reads and Writes

•

Temperature Ranges Supported:

Industrial (I):

-40C to +85C

Automotive (A3): -40C to +125C

•

RoHS Compliant

MAY 2018

DESCRIPTION

The

ISSI

IS62/65WVS2568GALL/GBLL are 2M bit Fast

Serial static RAMs organized as 256K bytes by 8 bits. It

is fabricated using

ISSI's

high-performance CMOS

technology.

The device is accessed via a simple Serial Peripheral

Interface (SPI) compatible serial bus. The bus signals

required are a clock input (SCK) plus separate data

in (SI) and data out (SO) lines. Access the device is

controlled through a Chip Select (CS#) input.

Additionally, SDI (Serial Dual Interface) and SQI

(Serial Quad Interface) is supported if your application

needs faster data rates.

This device also supports unlimited reads and writes to

the memory array.

The IS62/65WVS2568GALL/GBLL are available in the

standard packages including 8-pin SOIC, 8-pin TSSOP

and 24-ball TFBGA (6mm x 8mm).

8-pin SOIC, 8-pin TSSOP, and 24-ball TFBGA

packages

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A2

05/16/2018

IS62/65WVS2568GALL

IS62/65WVS2568GBLL

Chip Select (CS#)

A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. When the

device is deselected, SO goes to the high- impedance state, allowing multiple parts to s hare the same SPI bus.

After power-up, a low level on CS# is required, prior to any sequence being initiated.

Serial Clock (SCK)

The SCK is used to synchronize the communication between a master and Serial SRAM. Instructions, addresses

or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated

after the falling edge of the clock input.

Serial Output (SO: SPI mode)

The SO pin is used to transfer data out of the device. During a read cycle, data is shifted out on this pin after the falling edge of the

serial clock.

Serial Input (SI: SPI mode)

The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge

of the serial clock.

HOLD Function (HOLD#: SPI Mode, and SDI Mode)

The HOLD# pin is used to suspend transmission to Serial SRAM while in the middle of a serial sequence without having

to re-transmit the entire sequence over again. It must be held high any time this function is not being used. Once the

device is selected and a serial sequence is underway, the HOLD# pin may be pulled low to pause further serial

communication without resetting the serial sequence.

The HOLD# pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the

next SCK high-to-low transition. The device must remain selected during this sequence. The SI and SCK levels are

“don’t cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial

communication, HOLD# should be brought high while the SCK pin is low, otherwise serial communication will not be

resumed until the next SCK high-to-low transition.

The SO line will tri-state immediately upon a high-to low transition of the HOLD# pin, and will begin outputting again

Immediately upon a subsequent low- to-high transition of the HOLD pin, independent of the state of SCK.

Hold functionality is not available when operating in Quad SPI mode

Serial Input / Output Pins (SIO0, SIO1: SDI Mode)

The SIO0 and SIO1 pins are used for Dual SPI mode of operation (SISIO0, SO-->SIO1). Functionality of these I/O pins is shared

with SO and SI.

Serial Input / Output Pins (SIO0, SIO1, SIO2, SIO3: SQI Mode)

The SIO0 through SIO3 pins are used for Quad SPI mode of operation. Because of the shared functionality of these pins the HOLD#

feature is not available when using Quad SPI mode (Hold#

SIO3

in Quad SPI mode)

DNU/SIO2 (Do Not Use or SIO2)

Pin 3 is DNU (Do No Use) in SPI mode and SDI mode. SIO3 in SQI mode.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A2

05/16/2018

IS62/65WVS2568GALL

IS62/65WVS2568GBLL

FUNCTION DESCRIPTION

Serial SRAM is designed to interface directly with the Serial Peripheral Interface (SPI). It can also interface with Multi-

IO SPI interface (Dual SPI and Quad SPI).

The device contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in

on the rising edge of SCK. The CS# pin must be low for the entire operation.

All instructions, addresses and data are transferred MSB first, LSB last.

OPERATION MODE

The device has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes

of operation are Byte, Page and Sequential.

Byte Operation

Byte Operation is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/ write operations

are limited to only one byte. The Command followed by the 24-bit address is clocked into the device and the data to/from

the device is transferred on the next eight clocks.

Page Operation

Page Operation is selected when bits 7 and 6 in the MODE register are set to 10. The device has 8192 pages of 32

bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically

incremented internally). If the data being read or written reaches the page boundary, then the internal address counter

will increment to the start of the page.

Sequential Operation

Sequential Operation is selected when bits 7 and 6 in the MODE register are set to 01. Sequential operation allows the

entire array to be written to and read from. The internal address counter is automatically incremented and page

boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will

roll over to 0x00000.

WRITE MODE

Prior to any attempt to write data to the device, the device must be selected by bringing CS# low. Once the device

is selected, the Write command can be started by issuing a WRITE instruction, followed by the 24-bit address, with

the first six MSB’s of the address being a “don’t care” bit, and then the data to be written. A write is terminated by the

CS# being brought high.

If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The

Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data

will start to be overwritten.

If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the

Device. The internal Address Pointer is automatically incremented. When the Address Pointer reaches the highest

Address (3FFFFh), the address counter rolls over to (00000h). This allows the operation to continue indefinitely.

However previous data will be overwritten.

READ MODE

The device is selected by pulling CS# Low. Then 8 bit instruction is transmitted to the device followed by the

24 bit address, with the first seven MSB’s of the address being a “don’t care” bit.

After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted

out on the SO pin after predefined dummy cycles. If operating in Sequential mode, the data stored in the memory at the

next address can be read sequentially by continuing to provide clock pulses.

The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted

out. When the highest address is reached (3FFFFh), the address counter rolls over to address 00000h, allowing the

read cycle to be continued indefinitely. The read operation is terminated by raising the CS# pin.

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A2

05/16/2018

IS62WVS2568GBLL-45NLI-TR Related Products

	IS62WVS2568GBLL-45NLI-TR	IS62WVS2568GBLL-45NLI
Description	Static random access memory 2Mb 256Kx8 45MHz 2.2-3.6V Serial static random access memory	SRAM 2Mb 256Kx8 45MHz 2.2-3.6V Serial SRAM
Product Category	static random access memory	SRAM
Interface Type	Serial	Serial

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