GS82583ET18/36GK-675/625/550/500
260-Pin BGA
Commercial Temp
Industrial Temp
Features
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8Mb x 36 and 16Mb x 18 organizations available
675 MHz maximum operating frequency
675 MT/s peak transaction rate (in millions per second)
48 Gb/s peak data bandwidth (in x36 devices)
Common I/O DDR Data Bus
Non-multiplexed SDR Address Bus
One operation - Read or Write - per clock cycle
Burst of 2 Read and Write operations
3 cycle Read Latency
1.3V nominal core voltage
1.2V, 1.3V, or 1.5V HSTL I/O interface
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
288Mb SigmaDDR-IIIe™
Burst of 2 SRAM
Up to 675 MHz
1.3V V
DD
1.2V, 1.3V, or 1.5V V
DDQ
Clocking and Addressing Schemes
The GS82583ET18/36GK SigmaDDR-IIIe SRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IIIe B2
SRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 SRAM is always one address pin
less than the advertised index depth (e.g. the 16M x 18 has 8M
addressable index).
SigmaDDR-IIIe™ Family Overview
SigmaDDR-IIIe SRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
SRAMs. Although very similar to GSI's second generation of
networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),
these third generation devices offer several new features that
help enable significantly higher performance.
Parameter Synopsis
Speed Grade
-675
-625
-550
-500
Max Operating Frequency
675 MHz
625 MHz
550 MHz
500 MHz
Read Latency
3 cycles
3 cycles
3 cycles
3 cycles
V
DD
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
Rev: 1.07 12/2017
1/29
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ET18/36GK-675/625/550/500
16M x 18 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCH
(CFG)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
DQ17
V
SS
DQ16
V
SS
DQ15
DQ14
V
SS
CQ1
CQ1
V
SS
NU
IO
NU
IO
V
SS
NU
IO
V
SS
NU
IO
V
SS
V
DD
2
V
DDQ
NU
IO
V
DDQ
NU
IO
V
DDQ
NU
IO
NU
IO
V
DDQ
NU
IO
V
DDQ
V
SS
DQ13
V
DDQ
DQ12
DQ11
V
DDQ
DQ10
V
DDQ
DQ9
V
DDQ
3
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
9
PZT1
PZT0
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NC
(1152 Mb)
10
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
12
V
DDQ
DQ0
V
DDQ
DQ1
V
DDQ
DQ2
DQ3
V
DDQ
DQ4
V
DDQ
V
SS
NU
IO
V
DDQ
NU
IO
NU
IO
V
DDQ
NU
IO
V
DDQ
NU
IO
V
DDQ
13
V
DD
V
SS
NU
IO
V
SS
NU
IO
V
SS
NU
IO
NU
IO
V
SS
CQ0
CQ0
V
SS
DQ5
DQ6
V
SS
DQ7
V
SS
DQ8
V
SS
V
DD
MCL
NC
(RSVD)
ZQ
MCL
(SIOM)
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NC
(576 Mb)
MCL
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(x18)
V
DD
SA
V
SS
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(B2)
V
DDQ
MZT1
R/W
V
SS
CK
CK
V
SS
LD
MZT0
V
DDQ
V
SS
NC
(RSVD)
V
SS
TCK
TDO
V
DD
NC
(RSVD)
NC
(RSVD)
V
SS
TMS
TDI
MCL
ZT
MCL
MCL
Notes:
1. Pins 6B, 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
8. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.07 12/2017
2/29
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ET18/36GK-675/625/550/500
8M x 36 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCL
(CFG)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
DQ26
V
SS
DQ25
V
SS
DQ24
DQ23
V
SS
CQ1
CQ1
V
SS
DQ30
DQ29
V
SS
DQ28
V
SS
DQ27
V
SS
V
DD
2
V
DDQ
DQ35
V
DDQ
DQ34
V
DDQ
DQ33
DQ32
V
DDQ
DQ31
V
DDQ
V
SS
DQ22
V
DDQ
DQ21
DQ20
V
DDQ
DQ19
V
DDQ
DQ18
V
DDQ
3
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
9
PZT1
PZT0
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NC
(1152 Mb)
10
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
12
V
DDQ
DQ0
V
DDQ
DQ1
V
DDQ
DQ2
DQ3
V
DDQ
DQ4
V
DDQ
V
SS
DQ13
V
DDQ
DQ14
DQ15
V
DDQ
DQ16
V
DDQ
DQ17
V
DDQ
13
V
DD
V
SS
DQ9
V
SS
DQ10
V
SS
DQ11
DQ12
V
SS
CQ0
CQ0
V
SS
DQ5
DQ6
V
SS
DQ7
V
SS
DQ8
V
SS
V
DD
MCL
NC
(RSVD)
ZQ
MCL
(SIOM)
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NC
(576 Mb)
MCL
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
NU
I
(x18)
V
DD
SA
V
SS
V
DDQ
MZT1
R/W
V
SS
CK
CK
V
SS
LD
MZT0
V
DDQ
V
SS
NC
(RSVD)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(B2)
V
SS
TCK
TDO
V
DD
NC
(RSVD)
NC
(RSVD)
V
SS
TMS
TDI
MCL
ZT
MCL
MCL
Notes:
1. Pins 6B, 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
8. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.07 12/2017
3/29
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ET18/36GK-675/625/550/500
Pin Description
Symbol
SA
Description
Address
— Read or Write Address is registered on
CK.
Write/Read Data
— Registered on
KD
and
KD
during Write operations; aligned with
CQ
and
CQ
during Read operations.
DQ[17:0] - x18 and x36.
DQ[35:18] - x36 only.
Read Data Valid
— Driven high one half cycle before valid Read Data.
Primary Input Clocks
— Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks
— Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch Write Data (DQ[17:0] in x36, DQ[8:0] in x18).
KD1, KD1: latch Write Data (DQ[35:18] in x36, DQ[17:9] in x18).
Read Data Output Clocks
— Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
Load Enable
— Registered onCK.
LD = 0: Loads a new address and initiates a Read or Write operation.
LD = 1: Initiates a NOP operation.
Read / Write Enable
— Registered on
CK.
R/W = 0: initiates a Write operation when LD = 0.
R/W = 1: initiates a Read operation when LD = 0.
DLL Enable
— Weakly pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Reset
— Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Driver Impedance Control Resistor Input
— Must be connected to V
SS
through an external resistor RQ to
program driver impedance.
ODT Impedance Control Resistor Input
— Must be connected to V
SS
through an external resistor RT to
program ODT impedance.
ODT Mode Select
— Set the ODT state globally for all input groups. Must be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
ODT Configuration Select
— Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Type
Input
DQ[35:0]
I/O
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
LD
Output
Input
Input
Output
Input
R/W
Input
DLL
Input
RST
ZQ
ZT
Input
Input
Input
MZT[1:0]
Input
PZT[1:0]
Input
Rev: 1.07 12/2017
4/29
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583ET18/36GK-675/625/550/500
Symbol
MVQ
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
MCH
MCL
NC
Description
I/O Voltage Select
— Indicates what voltage is supplied to the V
DDQ
pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V or 1.3V nominal V
DDQ
.
MVQ = 1: Configure for 1.5V nominal V
DDQ
.
Core Power Supply
I/O Power Supply
Input Reference Voltage
— Input buffer reference voltage.
Ground
JTAG Clock
— Weakly pulled Low internally.
JTAG Mode Select
— Weakly pulled High internally.
JTAG Data Input
— Weakly pulled High internally.
JTAG Data Output
Must Connect High
— May be tied to V
DDQ
directly or via a 1k resistor.
Must Connect Low
— May be tied to V
SS
directly or via a 1k resistor.
No Connect
— There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input
— There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Input/Output
— There is an internal chip connection to these I/O pins, but they are unused by the
device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied/driven Low. They should not be tied/driven High.
Type
Input
—
—
—
—
Input
Input
Input
Output
Input
Input
—
NU
I
Input
NU
IO
I/O
Rev: 1.07 12/2017
5/29
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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