Features
•
•
•
•
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
20 MHz Clock Rate (5V)
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-
lead Ultra Thin SAP Packages
Lead-free/Halogen-free
Available in Automotive
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
•
•
•
•
•
•
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
•
•
•
•
AT25128A
AT25256A
Not
Recommended
for New Design
Description
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead SAP packages. In addition, the entire family is available in
2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
8-lead PDIP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
8-lead SOIC
1
2
3
4
8
7
6
5
CS
VCC
SO
HOLD
WP
SCK
GND
SI
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead Ultra Thin SAP
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
8-ball dBGA2
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
3368J–SEEPR–06/07
Bottom View
Bottom View
Table 0-1.
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Pin Configurations
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
Block Write protection is enabled by programming the status register with top ¼, top ½ or entire
array of write protection. Separate Program Enable and Program Disable instructions are pro-
vided for additional data protection. Hardware data protection is provided via the WP pin to
protect against inadvertent write attempts to the status register. The HOLD pin may be used to
suspend any serial communication without resetting the serial sequence.
1. Absolute Maximum Ratings*
Operating Temperature
55C
to +125C
Storage Temperature
65C
to +150C
Voltage on Any Pin
with Respect to Ground
1.0V
to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
2
AT25128A_256A
3368J–SEEPR–06/07
AT25128A_256A
Figure 1-1.
Block Diagram
16384/32768 x 8
Table 1-1.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
3
3368J–SEEPR–06/07
Analogue and Mixed Signal
京公网安备 11010802033920号
EEWORLD
