GS81302T07/10/19/37E-450/400/350/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
144Mb SigmaDDR
TM
-II+
Burst of 2 SRAM
450 MHz–300 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
SRAMs. The GS81302T07/10/19/37E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302T07/10/19/37E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
SigmaDDR™ Family Overview
The GS81302T07/10/19/37E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
Parameter Synopsis
-450
tKHKH
tKHQV
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.03b 8/2017
1/30
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Embedded System
京公网安备 11010802033920号
EEWORLD
