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GS81313HQ18GK-600I

Description
Static random access memory 1.5V 8M x 18 144M
Categorysemiconductor    Memory IC    Static random access memory   
File Size185KB,26 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
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GS81313HQ18GK-600I Overview

Static random access memory 1.5V 8M x 18 144M

GS81313HQ18GK-600I Parametric

Parameter NameAttribute value
MakerGSI Technology
Product Categorystatic random access memory
storage144 Mbit
organize8 M x 18
maximum clock frequency600 MHz
Interface TypeParallel
Supply voltage - max.1.35 V
Supply voltage - min.1.2 V
Supply current—max.1.5 A
Minimum operating temperature- 40 C
Maximum operating temperature+ 100 C
Installation styleSMD/SMT
Package/boxBGA-260
EncapsulationTray
storage typeDDR-III
seriesGS81313HQ18GK
typeSigmaQuad-IIIe B2
Factory packaging quantity10
GS81313HQ18/36GK-800/714/600
260-Pin BGA
Com & Ind Temp
HSTL I/O
Features
4Mb x 36 and 8Mb x 18 organizations available
800 MHz maximum operating frequency
1.6 BT/s peak transaction rate (in billions per second)
115 Gb/s peak data bandwidth (in x36 devices)
Separate I/O DDR Data Buses
Non-multiplexed DDR Address Bus
Two operations - Read and Write - per clock cycle
Burst of 2 Read and Write operations
3 cycle Read Latency
On-chip ECC with virtually zero SER
1.25V ~ 1.3V core voltage
1.5V HSTL I/O interface
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
144Mb SigmaQuad-IIIe™
Burst of 2 ECCRAM™
Clocking and Addressing Schemes
Up to 800 MHz
1.25V ~ 1.3V V
DD
1.5V V
DDQ
The GS81313HQ18/36GK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Parameter Synopsis
Speed Grade
-800
-714
-600
Max Operating Frequency
800 MHz
714 MHz
600 MHz
Read Latency
3 cycles
3 cycles
3 cycles
V
DD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.12 5/2016
1/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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