CY7C1041G
CY7C1041GE
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed
❐
t
AA
= 10 ns/15 ns
Embedded ECC for single-bit error correction
[1, 2]
Low active and standby currents
❐
Active current: I
CC
= 38 mA typical
❐
Standby current: I
SB2
= 6 mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
1.0-V data retention
TTL-compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
■
■
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O
0
through I/O
15
and address on A
0
through A
17
pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O
8
through I/O
15
and BLE controls I/O
0
through I/O
7
.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O
0
through I/O
15
). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
All I/Os (I/O
0
through I/O
15
) are placed in a high-impedance state
during the following events:
■
■
■
■
■
■
■
The device is deselected (CE HIGH)
The control signals (OE, BLE, BHE) are de-asserted
Functional Description
CY7C1041G and CY7C1041GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both devices are
offered in single chip-enable option and in multiple pin
configurations. The CY7C1041GE device includes an ERR pin
that signals an error-detection and correction event during a read
cycle.
On the CY7C1041GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)
[1]
. See the
Truth
Table on page 14
for a complete description of read and write
modes.
The logic block diagram is on page 2.
Product Portfolio
Product
[3]
Features and Options (see
Pin
Configurations on page 4)
Range
V
CC
Range
(V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
Power Dissipation
Speed
(ns) Operating I
CC
, (mA)
Standby, I
SB2
(mA)
f = f
max
10/15
Typ
[4]
Max
Typ
[4]
Max
15
10
10
–
38
38
40
45
45
6
8
CY7C1041G(E)18 Single Chip Enable
CY7C1041G(E)30
CY7C1041G(E)
Optional ERR pins
Industrial
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer
AN88889
for details.
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer
Ordering Information on page 15
for details.
4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a V
CC
range of 1.65 V–2.2 V),
V
CC
= 3 V (for a V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for a V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-91368 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 13, 2018
CY7C1041G
CY7C1041GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
AC Switching Characteristics ......................................... 9
Switching Waveforms .................................................... 10
Truth Table ...................................................................... 14
ERR Output – CY7C1041GE .......................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Document Number: 001-91368 Rev. *N
Page 3 of 21
CY7C1041G
CY7C1041GE
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable
without ERR, CY7C1041G
[5]
, Package/Grade ID: BVXI
[7]
with ERR, CY7C1041GE
[5, 6]
, Package/Grade ID: BVXI
[7]
1
BLE
I/O
0
I/O
1
VSS
VCC
I/O
6
I/O
7
NC
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
10
I/O
11
I/O
12
I/O
13
WE
A
11
6
NC
I/O
8
I/O
9
VCC
VSS
I/O
14
I/O
15
NC
1
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
3
A
0
A
3
A
5
A
17
ERR
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
10
I/O
11
I/O
12
I/O
13
WE
A
11
6
NC
I/O
8
I/O
9
VCC
VSS
I/O
14
I/O
15
NC
A
B
C
D
E
F
G
H
BLE
I/O
0
I/O
1
VSS
VCC
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm)
Single Chip Enable without ERR, CY7C1041G
[5]
,
Package/Grade ID: BVJXI
[7]
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm)
Single Chip Enable with ERR, CY7C1041GE
[5, 6]
,
Package/Grade ID: BVJXI
[7]
1
BLE
I/O
8
I/O
9
VSS
VCC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
VCC
VSS
I/O
6
I/O
7
NC
1
A
B
C
D
E
F
G
H
BLE
I/O
8
I/O
9
VSS
VCC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
ERR
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
VCC
VSS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Notes
5. NC pins are not connected internally to the die.
6. ERR is an output pin.
7. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O
[7:0]
and I/O
[15:8]
balls are swapped.
Document Number: 001-91368 Rev. *N
Page 4 of 21
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