IS34ML02G081
IS35ML02G081
2Gb SLC-1b ECC
3.3V X8 NAND FLASH MEMORY STANDARD NAND INTERFACE
IS34/35ML02G081
2Gb (x8) 3.3V NAND FLASH MEMORY with 1b ECC
FEATURES
Flexible & Efficient Memory
Architecture
- Organization: 256Mb x8
- Memory Cell Array: (256M + 8M) x 8bit
- Data Register: (2K + 64) x 8bit
- Page Size: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
- Memory Cell: 1bit/Memory Cell
Efficient Read and Program modes
- Command/Address/Data Multiplexed I/O
Interface
- Command Register Operation
- Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
- NOP: 4 cycles
- Cache Program Operation for High
Performance Program
- Cache Read Operation
- Copy-Back Operation
- EDO mode
- OTP operation
- Two-Plane Operation
-
Bad-Block-Protect
Highest performance
-
Read Performance
- Random Read: 25us (Max.)
- Serial Access: 25ns (Max.)
-
Write Performance
- Program time: 400us - typical
- Block Erase time: 2ms – typical
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-
-
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Low Power with Wide Temp. Ranges
Single 3.3V (2.7V to 3.6V) Voltage
Supply
15 mA Active Read Current
10 µA Standby Current
Temp Grades:
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
- Automotive, A1: -40°C to +85°C
- Automotive, A2: -40°C to +105°C
Reliable CMOS Floating Gate
Technology
ECC Requirement: X8 -
1bit/512Byte
Endurance: 100K Program/Erase cycles
Data Retention: 10 years
Advanced Security Protection
- Hardware Data Protection:
- Program/Erase Lockout during Power
Transitions
Industry Standard Pin-out & Packages
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T =48-pin TSOP (Type I )
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B =63-ball VFBGA
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Integrated Silicon Solution, Inc.- www.issi.com
Rev. A3
06/15/2018
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IS34/35ML02G081
GENERAL DESCRIPTION
The IS34/35ML2G081 is a 256Mx8bit with spare 8Mx8bit capacity. The device is offered in 3.3V Vcc
Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage
market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The device contains 2,048 blocks, composed by 64 pages consisting in two NAND structures of 32
series connected Flash cells. A program operation allows to write the 2,112-Byte page in typical 300us
and an erase operation can be performed in typical 3ms on a 128K-Byte for X8 device block.
Data in the page mode can be read out at 25ns cycle time per Word. The I/O pins serve as the ports for
address and command inputs as well as data input/output.
The copy back function allows the optimization of defective blocks management: when a page program
operation fails, the data can be directly programmed in another page inside the same array section
without the time consuming serial data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is
copied into the Flash array.
This pipelined program operation improves the program throughput when long files are written inside
the memory. A cache read feature is also implemented. This feature allows to dramatically improving
the read throughput when consecutive pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A3
06/15/2018
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IS34/35ML02G081
TABLE OF CONTENTS
FEATURES ............................................................................................................................................................ 2
GENERAL DESCRIPTION .................................................................................................................................... 3
TABLE OF CONTENTS ......................................................................................................................................... 4
1.
2.
3.
4.
5.
PIN CONFIGURATION ................................................................................................................................... 6
PIN DESCRIPTIONS ...................................................................................................................................... 8
BLOCK DIAGRAM .......................................................................................................................................... 9
OPERATION DESCRIPTION ....................................................................................................................... 11
ELECTRICAL CHARACTERISTICS............................................................................................................. 13
5.1 ABSOLUTE MAXIMUM RATINGS
(1)
..................................................................................................... 13
5.2 Recommended Operating Conditions .................................................................................................... 13
5.3 DC CHARACTERISTICs ........................................................................................................................ 14
5.4 Valid Block .............................................................................................................................................. 14
5.5 AC Measurement Condition .................................................................................................................... 15
5.6 AC PIN CAPACITANCE (TA = 25°C, VCC=3.3V, 1MHz) ...................................................................... 15
5.7 Mode Selection ....................................................................................................................................... 15
5.8 ROGRAM/ERASE PERFORMANCne .................................................................................................... 16
5.9 AC CHARACTERISTICS for address/ command/data input .................................................................. 16
5.10 AC CHARACTERISTICS for Operation ................................................................................................ 17
6.
TIMING DIAGRAMS ..................................................................................................................................... 18
6.1 Command Latch Cycle ........................................................................................................................... 18
6.2 Address Latch Cycle ............................................................................................................................... 18
6.3 Input Data Latch Cycle ........................................................................................................................... 19
6.4 Serial Access Cycle after Read (CLE=L, WE#=H, ALE=L) .................................................................... 19
6.5 Serial Access Cycle after Read (EDO Type CLE=L, WE#=H, ALE=L) .................................................. 20
6.6 Status Read Cycle .................................................................................................................................. 20
6.7 Read Operation (One PAGE) ................................................................................................................. 21
6.8 Read Operation (Intercepted by CE#) .................................................................................................... 21
6.9 Random Data Output In a Page ............................................................................................................. 22
6.10 Page program Operation ...................................................................................................................... 22
6.11 Page Program Operation with Random Data Input .............................................................................. 23
6.12 Copy-Back Operation with Random Data InpuT .................................................................................. 23
6.13 Cache Program Operation .................................................................................................................... 24
6.14 Block Erase Operation .......................................................................................................................... 24
6.15 Cache Read Operation ......................................................................................................................... 25
6.16 Read ID Operation ................................................................................................................................ 26
6.17 TWo-plane Page Read Operation with Two-Plane Random Data Out ................................................ 27
6.18 two-plane Cache Read Operation ........................................................................................................ 28
6.19 Two-plane Page Program Operation .................................................................................................... 29
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A3
06/15/2018
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IS34/35ML02G081
6.20 two-plane Cache Program Operation ................................................................................................... 30
6.21 READ Two Plane Block Erase Operation ............................................................................................. 31
7.
8.
ID Definition Table ........................................................................................................................................ 32
DEVICE OPERATION .................................................................................................................................. 34
8.1 Page READ OPERATION ...................................................................................................................... 34
8.2 Page Program ......................................................................................................................................... 36
8.3 Cache Program ....................................................................................................................................... 37
8.4 Copy-Back Program................................................................................................................................ 38
8.5 Block Erase ............................................................................................................................................. 39
8.6 Read Status ............................................................................................................................................ 39
8.7 Read ID ................................................................................................................................................... 41
8.8 Reset ....................................................................................................................................................... 42
8.9 Cache Read ............................................................................................................................................ 43
8.10 Two-Plane Page Read .......................................................................................................................... 44
8.11 Two-Plane Cache Read ........................................................................................................................ 45
8.12 Two-Plane Page Program .................................................................................................................... 46
8.13 Two-Plane Copy Back Program ........................................................................................................... 47
8.14 Two-Plane Cache Program .................................................................................................................. 49
8.15 Two-Plane Block Erase ........................................................................................................................ 50
8.16 Ready/Busy#......................................................................................................................................... 51
8.17 Data Protection and Power Up Sequence ............................................................................................ 52
8.18 Write Protect Operation ........................................................................................................................ 53
9.
INVALID BLOCK AND ERROR MANAGEMENT ......................................................................................... 55
9.1
Mask Out Initial Invalid Block(s)........................................................................................................... 55
9.2 Identifying Initial Invalid Block(s) and Block Replacement Management ............................................... 55
9.3 ERRor in Read or Write operation .......................................................................................................... 57
9.4 Addressing for PROGRAM operation ..................................................................................................... 62
9.5 System Interface Using CE# NOT Care operation ................................................................................. 63
10.
PACKAGE TYPE INFORMATION ........................................................................................................... 64
10.1 48-Pin TSOP (TYPE I) Package (T) ..................................................................................................... 64
10.2 63-BALL VFBGA Package (B) .............................................................................................................. 65
11.
ORDERING INFORMATION – Valid Part Numbers ................................................................................ 66
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A3
06/15/2018
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