AS4C32M16D2B-25BIN
AS4C32M16D2B-25BCN
32M x 16 bit DDRII Synchronous DRAM (SDRAM)
Advance (Rev. 1.0, DEC. /2017)
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: V
DD
& V
DDQ
= +1.8V
0.1V
Operating temperature:
T
C
= 0~85°C (Commercial)
T
C
= -40~95°C (Industrial)
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 400 MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
- DQS & DQS#
4 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5,
6
WRITE latency = READ latency - 1 t
CK
Burst lengths: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
Off-Chip Driver (OCD)
- Impedance Adjustment
- Adjustable data-output drive strength
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
- Average refresh period
7.8μs @ -40°C
≦T
C
≦
+85°C
3.9μs @ +85°C
＜T
C
≦
+95°C
Overview
The AS4C32M16D2B is a high-speed CMOS
Double-Data-Rate-Two (DDR2), synchronous dynamic
random-access memory (SDRAM) containing 512 Mbits
in a 16-bit wide data I/Os. It is internally configured as
a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/
Os.
The device is designed to comply with DDR2 DRAM
key features such as posted CAS# with additive
latency, Write latency = Read latency -1, Off-Chip
Driver (OCD) impedance adjustment, and On Die
Termination(ODT)
.
All of the control and address inputs are
synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and CK# falling).
All I/Os are synchronized with a pair of bidirectional
strobes (DQS and DQS#) in a source synchronous
fashion. The address bus is used to convey row,
column, and bank address information in RAS #,
CAS# multiplexing style. Accesses begin with the
registration of a Bank Activate command, and then it is
followed by a Read or Write command. Read and write
accesses to the DDR2 SDRAM are 4 or 8-bit burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Operating the four memory
banks in an interleaved fashion allows random access
operation to occur at a higher rate than is possible with
standard DRAMs. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. A sequential
and gapless data rate is possible depending on burst
length, CAS latency, and speed grade of the device.
84-ball 8x12.5x1.2mm (max) FBGA
- Pb and Halogen Free
Table 1. Ordering Information
Product part No.
AS4C32M16D2B-25BCN
AS4C32M16D2B-25BIN
Org
32M x 16
32M x 16
Temperature
Commercial 0°C to
85°C
Industrial -40°C to 95°C
Max Clock
(MHz)
400
400
Package
84-ball FBGA
84-ball FBGA
Table 2. Speed Grade Information
Speed Grade
DDR2-800
Clock Frequency
400MHz
CAS Latency
5
t
RCD
(ns)
12.5
t
RP
(ns)
12.5
Confidential
- 2 of 63 -
Rev.1.0. Dec. 2017
AS4C32M16D2B-25BIN
AS4C32M16D2B-25BCN
Figure 3. State Diagram
OCD
calibration
CKEL
Initialization
Sequence
PR
Setting
MR,
EMR(1)
EMR(2)
EMR(3)
Self
Refreshing
SRF
H
CKE
(E)MRS
Idle
All banks
precharged
REF
Refreshing
ACT
CK
EL
CK
EH
EL
CK
Precharge
Power
Down
Activating
CKEL
Active
Power
Down
CKE
L
CKEL
Automatic Sequence
Cammand Sequence
CKEH
CKE
L
WR
Writing
Bank
Active
RD
Reading
W
RA
WR
RD
WR
RD
A
RD
A
RDA
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down,exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
WRA
WR
Writing
With
Autoprecharge
PR, PRA
PR, PRA
RDA
PR, PRA
Reading
With
Autoprecharge
Precharging
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the
commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among
other things, are not captured in full detail.
Confidential
- 5 of 63 -
Rev.1.0. Dec. 2017
京公网安备 11010802033920号
EEWORLD
