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ispLSI 2032A-180LT48

Description
CPLD - Complex Programmable Logic Device USE ispMACH 4000V
Categorysemiconductor    Programmable logic IC    CPLD - complex programmable logic devices   
File Size406KB,17 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

ispLSI 2032A-180LT48 Overview

CPLD - Complex Programmable Logic Device USE ispMACH 4000V

ispLSI 2032A-180LT48 Parametric

Parameter NameAttribute value
MakerLattice
Product CategoryCPLD - Complex Programmable Logic Device
RoHSN
productispLSI 2032A
Large battery quantity32
Number of logical array blocks - LAB8
Maximum operating frequency200 MHz
Propagation Delay—Max.7.5 ns
Number of input/output terminals32 I/O
Working power voltage5 V
Minimum operating temperature0 C
Maximum operating temperature+ 70 C
Installation styleSMD/SMT
Package/boxTQFP-48
EncapsulationTray
high1 mm
length7 mm
storage typeEEPROM
seriesispLSI 1032/A
width7 mm
Number of gates1000
Working power current60 mA
Factory packaging quantity250
Supply voltage - max.5.25 V
Supply voltage - min.4.75 V
unit weight9.072 g
Lead-
Free
Package
Options
Available!
ispLSI 2032/A
In-System Programmable High Density PLD
Functional Block Diagram
®
Features
• ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging
— ispLSI 2032A is Built on an Advanced 0.35 Micron
E
2
CMOS
®
Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
S
A0
Output Routing Pool (ORP)
Select devices have been discontinued.
See Ordering Information section for product status.
D
ES
IG
D Q
1000 PLD Gates
32 I/O Pins, Two Dedicated Inputs
32 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
Input Bus
A2
GLB
Logic
Array
D Q
D Q
A5
D Q
f
max
= 180 MHz Maximum Operating Frequency
t
pd
= 5.0 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
N
EW
A3
A4
0139Bisp/2000
• IN-SYSTEM PROGRAMMABLE
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
U
SE
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
pL
SI
20
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
32
E
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
is
FO
The ispLSI 2032 and 2032A are High Density Program-
mable Logic Devices. The devices contain 32 Registers,
32 Universal I/O pins, two Dedicated Input Pins, three
Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2032 and 2032A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2032 and 2032A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
(Figure 1). There are a total of eight GLBs in the ispLSI
2032 and 2032A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
R
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
2032_11
1
Input Bus
A1
A6
Output Routing Pool (ORP)
Global Routing Pool
(GRP)
N
A7
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