74ABT827
10-bit buffer/line driver; non-inverting; 3-state
Rev. 5 — 7 November 2011
Product data sheet
1. General description
The 74ABT827 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT827 10-bit buffers provide high performance bus interface buffering for wide
data/address paths or buses carrying parity. They have NOR Output Enables (OE0, OE1)
for maximum control flexibility.
2. Features and benefits
Ideal where high speed, light loading, or increased fan-in are required
Flow-through pinout architecture for microprocessor oriented applications
Output capability: +64 mA and
32
mA
Power-up 3-state
Inputs are disabled during 3-state mode
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74ABT827D
74ABT827DB
74ABT827PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Name
SO24
SSOP24
TSSOP24
Description
Version
plastic small outline package; 24 leads; body width SOT137-1
7.5 mm
plastic shrink small outline package; 24 leads; body SOT340-1
width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
Type number
NXP Semiconductors
74ABT827
10-bit buffer/line driver; non-inverting; 3-state
4. Functional diagram
1
13
&
EN1
2
3
4
5
6
7
8
9
10 11
2
3
1
23
22
21
20
19
18
17
16
15
14
1
13
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
OE0
OE1
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
23 22 21 20 19 18 17 16 15 14
001aae885
4
5
6
7
8
9
10
11
001aae886
Fig 1.
Logic symbol
Fig 2.
IEEE/IEC logic symbol
A0
2
OE0
OE1
1
13
23
Y0
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
A9
11
22
Y1
21
Y2
20
Y3
19
Y4
18
Y5
17
Y6
16
Y7
15
Y8
14
Y9
001aae887
Fig 3.
Logic diagram
74ABT827
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
2 of 14
NXP Semiconductors
74ABT827
10-bit buffer/line driver; non-inverting; 3-state
5. Pinning information
5.1 Pinning
74ABT827
OE0
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
24 V
CC
23 Y0
22 Y1
21 Y2
20 Y3
19 Y4
18 Y5
17 Y6
16 Y7
15 Y8
14 Y9
13 OE1
001aae884
A8 10
A9 11
GND 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
OE0
A0 to A9
GND
OE1
Y0 to Y9
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
12
13
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
24
Description
output enable input (active LOW)
data input
ground (0 V)
output enable input (active LOW)
data output
supply voltage
6. Functional description
6.1 Function table
Table 3.
Inputs
OEn
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don t care;
Z = high-impedance OFF-state.
74ABT827
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Function table
[1]
Output
An
L
H
X
Yn
L
H
Z
transparent
transparent
high-impedance
Operating mode
Product data sheet
Rev. 5 — 7 November 2011
3 of 14
NXP Semiconductors
74ABT827
10-bit buffer/line driver; non-inverting; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
32
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
64
5
+85
Unit
V
V
V
V
mA
mA
ns/V
C
74ABT827
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
4 of 14
NXP Semiconductors
74ABT827
10-bit buffer/line driver; non-inverting; 3-state
9. Static characteristics
Table 6.
Static characteristics
Conditions
Min
V
IK
V
OH
input clamping voltage
HIGH-level output
voltage
V
CC
= 4.5 V; I
IK
=
18
mA
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
=
3
mA
V
CC
= 5.0 V; I
OH
=
3
mA
V
CC
= 4.5 V; I
OH
=
32
mA
V
OL
I
I
I
OFF
I
O(pu/pd)
I
OZ
LOW-level output
voltage
input leakage current
power-off leakage
current
power-up/power-down
output current
V
CC
= 4.5 V; I
OL
= 64 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 0 V; V
I
or V
O
4.5 V
V
CC
= 2.0 V; V
O
= 0.5 V;
V
I
= GND or V
CC
; OEn HIGH
V
O
= 2.7 V
V
O
= 0.5 V
I
LO
I
O
I
CC
output leakage current
output current
supply current
HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
outputs HIGH-state
outputs LOW-state
outputs disabled
I
CC
additional supply current per input pin; V
CC
= 5.5 V; one
input at 3.4 V; other inputs at
V
CC
or GND
outputs enabled
outputs 3-state, one data
input
outputs 3-state; one enable
input
C
I
C
O
input capacitance
output capacitance
V
I
= 0 V or V
CC
outputs disabled; V
O
= 0 V
or V
CC
[3]
[2]
[1]
Symbol Parameter
25
C
Typ
0.9
2.9
3.4
2.4
0.42
0.01
5.0
5.0
Max
-
-
-
-
0.55
1.0
100
50
1.2
2.5
3.0
2.0
-
-
-
-
40 C
to +85
C
Unit
Min
1.2
2.5
3.0
2.0
-
-
-
-
Max
-
-
-
-
0.55
1.0
100
50
V
V
V
V
V
A
A
A
OFF-state output current V
CC
= 5.5 V; V
I
= V
IL
or V
IH
-
-
-
180
-
-
-
5.0
5.0
5.0
80
0.5
25
0.5
50
50
50
50
250
38
250
-
-
-
180
-
-
-
50
50
50
50
250
38
250
A
A
A
mA
A
mA
A
-
-
-
-
-
0.5
0.01
0.5
4
7
1.5
50
1.5
-
-
-
-
-
-
-
1.5
50
1.5
-
-
mA
mA
mA
pF
pF
[1]
[2]
[3]
This parameter is valid for any V
CC
between 0 V and 2.1 V with a transition time of up to 10 ms. For V
CC
= 2.1 V to V
CC
= 5 V
10 %, a
transition time of up to 100
s
is permitted.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
74ABT827
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 7 November 2011
5 of 14
京公网安备 11010802033920号
EEWORLD
