BX80677I37100S R35C datasheet, PDF

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BX80677I37100S R35C: DescriptionCPU - Boxed Intel Core i3-7100 Processor (3M Cache, 3.90 GHz) FC-LGA14C, Box; Categorysemiconductor The embedded processor and controller CPU - the central processor; File Size3MB，127 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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BX80677I37100S R35C Overview

CPU - Boxed Intel Core i3-7100 Processor (3M Cache, 3.90 GHz) FC-LGA14C, Box

BX80677I37100S R35C Parametric

Parameter Name	Attribute value
Maker	Intel
Product Category	CPU - central processing unit
Encapsulation	Bulk
series	i3-7100
Factory packaging quantity	5

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7th Generation Intel

Processor

Families for S Platforms

and Intel

Core™ X-Series Processor Family

Datasheet, Volume 1 of 2

Supporting 7th Generation Intel

Core™ Processor Families, Intel

Pentium

Processors and Intel

Celeron

Processors Family for

S Platforms Intel

Celeron

Processors and Intel

Core™ X-Series

Processor Platforms, formerly known as Kaby Lake

December 2018

Revision 003

Document Number: 335195-003

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel

products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted

which includes subject matter disclosed herein.

No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.

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activation. Performance varies depending on system configuration.

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Check with

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or retailer.

The products described may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

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a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or

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*Other names and brands may be claimed as the property of others.

Datasheet, Volume 1 of 2

Contents

Introduction

............................................................................................................ 11

1.1

Supported Technologies ..................................................................................... 13

1.2

Power Management Support ............................................................................... 13

1.2.1 Processor Core Power Management........................................................... 13

1.2.2 System Power Management ..................................................................... 13

1.2.3 Memory Controller Power Management...................................................... 14

1.2.4 Processor Graphics Power Management ..................................................... 14

1.2.4.1 Memory Power Savings Technologies ........................................... 14

1.2.4.2 Display Power Savings Technologies ............................................ 14

1.2.4.3 Graphics Core Power Savings Technologies................................... 14

1.3

Thermal Management Support ............................................................................ 14

1.4

Package Support ............................................................................................... 15

1.5

Processor Testability .......................................................................................... 15

1.6

Operating Systems Support................................................................................ 15

Terminology ..................................................................................................... 15

1.7

Related Documents ........................................................................................... 17

1.8

Interfaces................................................................................................................

2.1

System Memory Interface .................................................................................. 19

2.1.1 System Memory Technology Supported ..................................................... 19

2.1.1.1 DDR3L/-RS Supported Memory Modules and Devices ..................... 20

2.1.1.2 DDR4 Supported Memory Modules and Devices............................. 21

2.1.2 System Memory Timing Support............................................................... 22

2.1.3 System Memory Organization Modes......................................................... 22

2.1.4 System Memory Frequency...................................................................... 23

2.1.5 Technology Enhancements of Intel

Fast Memory Access (Intel

FMA).......... 24

2.1.6 Data Scrambling .................................................................................... 24

2.1.7 DDR I/O Interleaving .............................................................................. 24

2.1.8 Data Swapping ...................................................................................... 26

2.1.9 DRAM Clock Generation........................................................................... 26

2.1.10 DRAM Reference Voltage Generation ......................................................... 26

2.1.11 Data Swizzling ....................................................................................... 26

2.2

PCI Express* Graphics Interface (PEG)................................................................. 26

2.2.1 PCI Express* Support ............................................................................. 26

2.2.2 PCI Express* Architecture ....................................................................... 28

2.2.3 PCI Express* Configuration Mechanism ..................................................... 29

2.2.4 PCI Express* Equalization Methodology ..................................................... 29

2.3

Direct Media Interface (DMI)............................................................................... 30

2.3.1 DMI Error Flow....................................................................................... 30

2.3.2 DMI Link Down ...................................................................................... 30

2.4

Processor Graphics ............................................................................................ 30

2.4.1

2.4.2

API Support (Windows*) ......................................................................... 31

Media Support (Intel

QuickSync & Clear Video Technology HD) .................. 31

2.4.2.1 Hardware Accelerated Video Decode............................................ 31

2.4.2.2 Hardware Accelerated Video Encode ............................................ 32

2.4.2.3 Hardware Accelerated Video Processing ....................................... 33

2.4.2.4 Hardware Accelerated Transcoding .............................................. 33

Camera Pipe Support .............................................................................. 33

Switchable/Hybrid Graphics ..................................................................... 34

Gen 9 LP Video Analytics ......................................................................... 34

Gen 9 LP (9th Generation Low Power) Block Diagram .................................. 35

2.4.3

2.4.4

2.4.5

2.4.6

Datasheet, Volume 1 of 2

2.5

2.6

2.4.7 GT2 Graphic Frequency ...........................................................................35

Display Interfaces ..............................................................................................36

2.5.1 DisplayPort* ..........................................................................................39

2.5.2 High-Definition Multimedia Interface (HDMI*).............................................40

2.5.3 Digital Video Interface (DVI) ....................................................................41

2.5.4 embedded DisplayPort* (eDP*) ................................................................41

2.5.5 Integrated Audio ....................................................................................41

2.5.6 Multiple Display Configurations (Dual Channel DDR) ....................................42

2.5.7 Multiple Display Configurations (Single Channel DDR) ..................................43

2.5.8 High-bandwidth Digital Content Protection (HDCP) ......................................43

2.5.9 Display Link Data Rate Support ................................................................44

2.5.10 Display Bit Per Pixel (BPP) Support............................................................45

2.5.11 Display Resolution per Link Width .............................................................45

Platform Environmental Control Interface (PECI) ....................................................45

2.6.1 PECI Bus Architecture..............................................................................46

Technologies............................................................................................................48

3.1

Intel

Virtualization Technology (Intel

VT) ..........................................................48

3.1.1 Intel

Virtualization Technology (Intel

VT) for IA-32, Intel

64 and Intel

Architecture (Intel

VT-X) .......................................................................48

3.1.2 Intel

Virtualization Technology (Intel

VT) for Directed I/O (Intel

VT-d).....50

3.2

Security Technologies.........................................................................................53

3.2.1 Intel

Trusted Execution Technology (Intel

TXT) .......................................53

3.2.2 Intel

Advanced Encryption Standard New Instructions (Intel

AES-NI) .........54

3.2.3 PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction .........54

3.2.4 Intel

Secure Key ...................................................................................54

3.2.5 Execute Disable Bit .................................................................................55

3.2.6 Boot Guard Technology ...........................................................................55

3.2.7 Intel

Supervisor Mode Execution Protection (SMEP) ...................................55

3.2.8 Intel

Supervisor Mode Access Protection (SMAP) .......................................55

3.2.9 Intel

Memory Protection Extensions (Intel

MPX)......................................56

3.2.10 Intel

Software Guard Extensions (Intel

SGX) ..........................................56

3.2.11 Intel

Virtualization Technology (Intel

VT) for Directed I/O (Intel

VT-d).....57

3.3

Power and Performance Technologies ...................................................................57

3.3.1 Intel

Hyper-Threading Technology (Intel

HT Technology) .........................57

3.3.2 Intel

Turbo Boost Technology 2.0............................................................57

3.3.2.1 Intel

Turbo Boost Technology 2.0 Frequency ...............................57

3.3.3 Intel

Advanced Vector Extensions 2 (Intel

AVX2) ....................................58

3.3.4 Intel

64 Architecture x2APIC ..................................................................58

3.3.5 Power Aware Interrupt Routing (PAIR).......................................................59

3.3.6 Intel

Transactional Synchronization Extensions (Intel

TSX-NI) ..................60

3.4

Debug Technologies ...........................................................................................60

3.4.1 Intel

Processor Trace ............................................................................60

Power Management

.................................................................................................61

4.1

Advanced Configuration and Power Interface (ACPI) States Supported ......................63

4.2

Processor IA Core Power Management ..................................................................65

4.2.1 OS/HW controlled P-states .......................................................................65

4.2.1.1 Enhanced Intel

SpeedStep

Technology .....................................65

4.2.1.2 Intel

Speed Shift Technology ....................................................66

4.2.2 Low-Power Idle States.............................................................................66

4.2.3 Requesting Low-Power Idle States ............................................................67

4.2.4 Processor IA Core C-State Rules ...............................................................67

4.2.5 Package C-States ...................................................................................69

4.2.6 Package C-States and Display Resolutions..................................................71

4.3

Integrated Memory Controller (IMC) Power Management.........................................73

Datasheet, Volume 1 of 2

4.4

4.5

4.6

4.7

Disabling Unused System Memory Outputs ................................................ 73

DRAM Power Management and Initialization ............................................... 73

4.3.2.1 Initialization Role of CKE ............................................................ 74

4.3.2.2 Conditional Self-Refresh ............................................................ 74

4.3.2.3 Dynamic Power-Down................................................................ 75

4.3.2.4 DRAM I/O Power Management .................................................... 75

4.3.3 DDR Electrical Power Gating (EPG) ........................................................... 75

4.3.4 Power Training....................................................................................... 76

PCI Express* Power Management ........................................................................ 76

Direct Media Interface (DMI) Power Management .................................................. 76

Processor Graphics Power Management ................................................................ 77

4.6.1 Memory Power Savings Technologies ........................................................ 77

4.6.1.1 Intel

Rapid Memory Power Management (Intel

RMPM) ............... 77

4.6.1.2 Intel

Smart 2D Display Technology (Intel

S2DDT) ..................... 77

4.6.2 Display Power Savings Technologies ......................................................... 77

4.6.2.1 Intel

(Seamless & Static) Display Refresh Rate

Switching (DRRS) with eDP* Port ................................................ 77

4.6.2.2 Intel

Automatic Display Brightness ............................................ 77

4.6.2.3 Smooth Brightness.................................................................... 78

4.6.2.4 Intel

Display Power Saving Technology (Intel

DPST) 6.0 ............ 78

4.6.2.5 Panel Self-Refresh 2 (PSR 2) ...................................................... 78

4.6.2.6 Low-Power Single Pipe (LPSP) .................................................... 78

4.6.3 Processor Graphics Core Power Savings Technologies.................................. 79

4.6.3.1 Intel

Graphics Dynamic Frequency ............................................ 79

4.6.3.2 Intel

Graphics Render Standby Technology (Intel

GRST) ............ 79

4.6.3.3 Dynamic FPS (DFPS) ................................................................. 79

Voltage Optimization ......................................................................................... 79

4.3.1

4.3.2

Thermal Management

.............................................................................................. 80

5.1

Processor Thermal Management .......................................................................... 80

5.1.1 Thermal Considerations........................................................................... 80

5.1.2 Intel

Turbo Boost Technology 2.0 Power Monitoring .................................. 81

5.1.3 Intel

Turbo Boost Technology 2.0 Power Control ....................................... 81

5.1.3.1 Package Power Control .............................................................. 81

5.1.3.2 Platform Power Control .............................................................. 82

5.1.3.3 Turbo Time Parameter (Tau) ...................................................... 83

5.1.4 Configurable TDP (cTDP) and Low-Power Mode........................................... 83

5.1.4.1 Configurable TDP ...................................................................... 83

5.1.4.2 Low-Power Mode ...................................................................... 84

5.1.5 Thermal Management Features ................................................................ 84

5.1.5.1 Adaptive Thermal Monitor .......................................................... 84

5.1.5.2 Digital Thermal Sensor .............................................................. 87

5.1.5.3 PROCHOT# Signal..................................................................... 87

5.1.5.4 Bi-Directional PROCHOT# .......................................................... 88

5.1.5.5 Voltage Regulator Protection using PROCHOT# ............................. 88

5.1.5.6 Thermal Solution Design and PROCHOT# Behavior ........................ 88

5.1.5.7 Low-Power States and PROCHOT# Behavior ................................. 89

5.1.5.8 THERMTRIP# Signal .................................................................. 89

5.1.5.9 Critical Temperature Detection ................................................... 89

5.1.5.10 On-Demand Mode ..................................................................... 89

5.1.5.11 MSR Based On-Demand Mode..................................................... 89

5.1.5.12 I/O Emulation-Based On-Demand Mode ....................................... 90

5.1.6 Intel

Memory Thermal Management ........................................................ 90

5.1.7 Scenario Design Power (SDP)................................................................... 90

5.2

Thermal and Power Specifications........................................................................ 91

5.2.1 S-Processor Line Thermal and Power Specifications..................................... 92

5.2.1.1 Thermal Profile for PCG 2015D Processor ..................................... 95

5.2.1.2 Thermal Profile for PCG 2015C Processor ..................................... 96

Datasheet, Volume 1 of 2

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