S27KL0641/S27KS0641
S70KL1281/S70KS1281
3.0 V/1.8 V, 64 Mb (8 MB)/128 Mb (16 MB),
HyperRAM™ Self-Refresh DRAM
Distinctive Characteristics
HyperRAM™ Low Signal Count Interface
■
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■
■
■
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■
Up to 333 MBps
Double-Data Rate (DDR) - two data transfers per clock
166 MHz clock rate (333 MBps) at 1.8 V V
CC
100 MHz clock rate (200 MBps) at 3.0 V V
CC
Sequential burst transactions
Configurable Burst Characteristics
❐
Wrapped burst lengths:
• 16 bytes (8 clocks)
• 32 bytes (16 clocks)
• 64 bytes (32 clocks)
• 128 bytes (64 clocks)
❐
Linear burst
❐
Hybrid option - one wrapped burst followed by linear burst
❐
Wrapped or linear burst type selected in each transaction
❐
Configurable output drive strength
Low Power Modes
❐
Deep Power Down
Package
❐
24-ball FBGA
3.0 V I/O, 11 bus signals
❐
Single ended clock (CK)
1.8 V I/O, 12 bus signals
❐
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
❐
Bidirectional Data Strobe / Mask
❐
Output at the start of all transactions to indicate refresh la-
tency
❐
Output during read transactions as Read Data Strobe
❐
Input during write transactions as Write Data Mask
RWDS DCARS Timing
❐
During read transactions RWDS is offset by a second clock,
phase shifted from CK
❐
The Phase Shifted Clock is used to move the RWDS transi-
tion edge within the read data eye
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High Performance
■
Performance Summary
Read Transaction Timings
Maximum Clock Rate at 1.8 V V
CC
/V
CC
Q
Maximum Clock Rate at 3.0 V V
CC
/V
CC
Q
Maximum Access Time, (t
ACC
at 166 MHz)
Maximum CS# Access Time to first word at
166 MHz (excluding refresh latency)
166 MHz
100 MHz
36 ns
56 ns
Maximum Current Consumption
Burst Read or Write (linear burst at 166 MHz, 1.8 V)
Power On Reset
Standby (CS# = HIGH, 3.0 V, 105 °C)
Deep Power Down (CS# = HIGH, 3.0 V, 105 °C)
Standby (CS# = HIGH, 1.8 V, 105 °C)
Deep Power Down (CS# = HIGH, 1.8 V, 105 °C)
64 MB
60 mA
50 mA
300 µA
40 µA
300 µA
20 µA
128 MB
72 mA
100 mA
600 µA
N/A
600 µA
N/A
Cypress Semiconductor Corporation
Document Number: 001-97964 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 31, 2018
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Logic Block Diagrams
Block Diagram — 64 Mb
CS#
CK/CK#
RWDS
I/O
DQ[7:0]
RESET#
Data Path
Control
Logic
Y Decoders
Data Latch
X Decoders
Memory
Block Diagram — 128 Mb
HyperRAM 1
CS#
CK/CK#
RWDS
CS#
CK/CK#
RWDS
I/O
Control
Logic
X Decoders
Memory
Y Decoders
Data Latch
DQ[7:0]
DQ[7:0]
RESET#
Data Path
HyperRAM 2
CS#
CK/CK#
RWDS
I/O
DQ[7:0]
RESET#
Control
Logic
X Decoders
Memory
Y Decoders
Data Latch
RESET#
Data Path
Document Number: 001-97964 Rev. *L
Page 2 of 51
S27KL0641/S27KS0641
S70KL1281/S70KS1281
HyperRAM Block Diagram
HyperRAM Connections, Including Optional Signals
Master
V
CC
V
CC
Q
CS0#
CK
CK#
DQ[7:0]
RWDS
CS1#
RESET#
Slave 0
CS#
CK
CK#
DQ[7:0]
RWDS
V
CC
V
CC
Q
RESET#
64 Mbit
V
SS
V
SS
Q
V
SS
V
SS
Q
Slave 1
CS#
CK
CK#
DQ[7:0]
RWDS
V
CC
V
CC
Q
RESET#
64 Mbit
V
SS
V
SS
Q
Document Number: 001-97964 Rev. *L
Page 3 of 51
S27KL0641/S27KS0641
S70KL1281/S70KS1281
Contents
1.
2.
3.
General Description.....................................................
5
Product Overview
........................................................ 8
Signal Descriptions
..................................................... 9
3.1 Input/Output Summary .......................................... 9
3.2 Command/Address Bit Assignments................... 10
3.3 Read Transactions .............................................. 14
3.4 Write Transactions with Initial Latency
(Memory Core Write)........................................... 15
3.5 Write Transactions without Initial
Latency (Register Write) ..................................... 17
Memory Space............................................................
18
Register Space
........................................................... 18
5.1 Device Identification Registers ............................ 19
5.2 Register Space Access ....................................... 20
Interface States
.......................................................... 26
6.1 Power Conservation Modes ................................ 27
Electrical Specifications............................................
7.1 Absolute Maximum Ratings.................................
7.2 Latchup Characteristics.......................................
7.3 Operating Ranges ...............................................
7.4 DC Characteristics ..............................................
7.5 Power-Up Initialization.........................................
7.6 Power Down ........................................................
7.7 Hardware Reset ..................................................
28
28
29
29
30
32
33
34
11.
8.
Timing Specifications.................................................
35
8.1 Key to Switching Waveforms ............................... 35
8.2 AC Test Conditions .............................................. 35
8.3 AC Characteristics ............................................... 36
Physical Interface
....................................................... 39
9.1 FBGA 24-Ball 5 x 5 Array Footprint...................... 39
9.2 Physical Diagrams ............................................... 40
DDR Center Aligned Read Strobe
(DCARS) Functionality
............................................... 41
10.1 HyperRAM Products with DCARS
Signal Descriptions .............................................. 41
10.2 HyperRAM Products with DCARS
— FBGA 24-ball, 5 x 5 Array Footprint ................ 42
10.3 HyperRAM Memory with DCARS Timing ............. 42
Ordering Information
.................................................. 44
11.1 Ordering Part Number.......................................... 44
11.2 Valid Combinations .............................................. 45
11.3 Valid Combinations — Automotive Grade
/ AEC-Q100.......................................................... 47
9.
10.
4.
5.
6.
7.
12. Revision History..........................................................
49
Sales, Solutions, and Legal Information ...........................51
Worldwide Sales and Design Support ........................... 51
Products ........................................................................ 51
PSoC® Solutions .......................................................... 51
Cypress Developer Community ..................................... 51
Technical Support ......................................................... 51
Document Number: 001-97964 Rev. *L
Page 4 of 51
S27KL0641/S27KS0641
S70KL1281/S70KS1281
1.
General Description
The Cypress
®
64-Mb HyperRAM
™
device is a high-speed CMOS, self-refresh Dynamic RAM (DRAM), with a HyperBus interface.
The Cypress 128-Mb HyperRAM is a dual-die stack of 64-Mb HyperRAM devices in a single package.
The Random Access Memory (RAM) array uses dynamic cells that require periodic refresh. Refresh control logic within the device
manages the refresh operations on the RAM array when the memory is not being actively read or written by the HyperBus interface
master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the
memory uses static cells that retain data without refresh. Hence, the memory can also be described as Pseudo Static RAM (PSRAM).
Because the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host not perform read
or write burst transfers that are long enough to block the necessary internal logic refresh operations when they are needed. The host
is required to limit the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the
memory indicates a refresh operation is needed.
HyperBus is a low-signal-count, Double Data Rate (DDR) interface that achieves high-speed read and write throughput. The DDR
protocol transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on HyperBus consists of
a series of 16-bit wide, one clock cycle data transfers at the internal HyperRAM core with two corresponding 8-bit wide,
one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Ordering Part Number (OPN)
device versions are available for core (V
CC
) and IO buffer (V
CC
Q) supplies of either 1.8 V or 3.0 V (nominal).
Command, address, and data information is transferred over the eight HyperBus DQ[7:0] signals. The clock is used for information
capture by a HyperBus slave device when receiving command, address, or data on the DQ signals. Command or Address values are
center aligned with clock transitions.
Every transaction begins with the assertion of CS# and Command-Address (CA) signals, followed by the start of clock transitions to
transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is deasserted.
Figure 1. Read Transaction, Single Initial Latency Count
CS#
t
RWR
=Read Write Recovery
CK#,CK
Latency Count
RWDS
High = 2x Latency Count
Low = 1x Latency Count
RWDS and Data
are edge aligned
DQ[7:0]
47:40
39:32
31:24
23:16
15:8
7:0
Dn
A
Dn
B
Dn+1
A
Dn+1
B
t
ACC
= Access
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
Memory drives DQ[7:0]
and RWDS
The Read/Write Data Strobe (RWDS) is a bidirectional signal that indicates:
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when data will start to transfer from a HyperRAM device to the master device in read transactions (initial read latency)
when data is being transferred from a HyperRAM device to the master device during read transactions (as a source synchronous
read data strobe)
when data may start to transfer from the master device to a HyperRAM device in write transactions (initial write latency)
data masking during write data transfers
During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HyperRAM device to indicate whether
additional initial access latency is needed in the transaction.
During read data transfers, RWDS is a read data strobe with data values edge aligned with the transitions of RWDS.
Document Number: 001-97964 Rev. *L
Page 5 of 51
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