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IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level
translator with EMI filter and ESD protection
Rev. 2 — 15 October 2014
Product data sheet
1. General description
The device is an SD 3.0-compliant 6-bit bidirectional dual voltage level translator. It is
designed to interface between a memory card operating at 1.8 V or 2.9 V signal levels and
a host with a fixed nominal supply voltage of 1.7 V to 3.6 V. The device supports SD 3.0,
SDR104, SDR50, DDR50, SDR25, SDR12 and SD 2.0 high-speed (50 MHz) and
default-speed (25 MHz) modes. The device has an integrated voltage selectable low
dropout regulator to supply the card-side I/Os, built-in EMI filters and robust ESD
protections (IEC 61000-4-2, level 4).
2. Features and benefits
Supports up to 208 MHz clock rate
Feedback channel for clock synchronization
SD 3.0 specification-compliant voltage translation to support SDR104, SDR50,
DDR50, SDR25, SDR12, high-speed and default-speed modes
100 mA low dropout voltage regulator to supply the card-side I/Os
Low power consumption by push-pull output stage with break-before-make
architecture
Integrated pull-up and pull-down resistors: no external resistors required
Integrated EMI filters suppress higher harmonics of digital I/Os
Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side
Level shifting buffers keep ESD stress away from the host (zero-clamping concept)
25-ball WLCSP; pitch 0.4 mm
3. Applications
Smartphones
Mobile handsets
Digital cameras
Tablet PCs
Laptop computers
SD, MMC or microSD card readers
4. Ordering information
Table 1.
Ordering information
Package
Name
IP4856CX25/C
WLCSP25
Description
wafer level chip-size package with back side coating;
25 bumps (5
5); typical size: 2.05 mm
2.05 mm
0.51 mm
Version
-
Type number
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
5. Block diagram
Fig 1.
Block diagram
IP4856CX25_C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2014
2 of 21
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
6. Functional diagram
Fig 2.
Functional diagram
IP4856CX25_C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2014
3 of 21
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
7. Pinning information
7.1 Pinning
bump A1
index area
1
2
3
4
5
A
B
C
D
E
aaa-015216
transparent top view,
solder balls facing down
Fig 3.
Table 2.
A1
B1
C1
D1
E1
Pin configuration WLCSP25
Pin allocation table
Pin Symbol
A2
B2
C2
D2
E2
DIR_CMD
SEL
ENABLE
CMD_H
CLK_FB
Pin Symbol
A3
B3
C3
D3
E3
DIR_0
V
CCA
GND
CD
DIR_1_3
Pin Symbol
A4
B4
C4
D4
E4
V
SUPPLY
V
LDO
V
SD_REF
CMD_SD
WP
Pin Symbol
A5
B5
C5
D5
E5
DATA2_SD
DATA3_SD
CLK_SD
DATA0_SD
DATA1_SD
Pin Symbol
DATA2_H
DATA3_H
CLK_IN
DATA0_H
DATA1_H
7.2 Pin description
Table 3.
Symbol
[1]
DATA2_H
DIR_CMD
DIR_0
V
SUPPLY
DATA2_SD
DATA3_H
SEL
V
CCA
V
LDO
DATA3_SD
Pin description
Pin
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
Type
[2]
I/O
I
I
S
I/O
I/O
I
S
O
I/O
Description
data 2 input or output on host side
direction control input for command
direction control input for data 0
supply voltage (from battery or regulator)
data 2 input or output on memory card side
data 3 input or output on host side
card side I/O voltage level select
supply voltage from host side
internal supply decoupling
data 3 input or output on memory card side
IP4856CX25_C
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2 — 15 October 2014
4 of 21