1SX250LN2F43I1VG datasheet, PDF

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1SX250LN2F43I1VG: DescriptionFPGA - Field Programmable Gate Array; Categorysemiconductor Programmable logic IC The FPGA - field programmable gate array (FPGA); File Size329KB，38 Pages; ManufacturerAltera (Intel); Environmental Compliance

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FPGA - Field Programmable Gate Array

1SX250LN2F43I1VG Parametric

Parameter Name	Attribute value
Maker	Altera (Intel)
Product Category	FPGA - Field Programmable Gate Array
Shipping restrictions	This product may require additional documentation for export from the United States.
product	Stratix 10 SX
Number of logic elements	2500000
Number of logical array blocks - LAB	312500
Number of input/output terminals	688 I/O
Working power voltage	0.85 V
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 100 C
Installation style	SMD/SMT
Package/box	FBGA-1760
Encapsulation	Tray
data rate	28.3 Gb/s
series	Stratix 10 SX
Distributed RAM	256 kB
Maximum operating frequency	1 GHz
Transceiver quantity	48 Transceiver
Factory packaging quantity	12

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Stratix 10 GX/SX Device Overview

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S10-OVERVIEW | 2018.08.08

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Contents

1. Intel

Stratix

10 GX/SX Device Overview.................................................................... 3

1.1. Intel Stratix 10 Family Variants...............................................................................4

1.1.1. Available Options....................................................................................... 6

1.2. Innovations in Intel Stratix 10 FPGAs and SoCs......................................................... 6

1.3. FPGA and SoC Features Summary...........................................................................8

1.4. Intel Stratix 10 Block Diagram............................................................................... 11

1.5. Intel Stratix 10 FPGA and SoC Family Plan..............................................................11

1.6. HyperFlex Core Architecture.................................................................................. 15

1.7. Heterogeneous 3D SiP Transceiver Tiles.................................................................. 16

1.8. Intel Stratix 10 Transceivers................................................................................. 17

1.8.1. PMA Features......................................................................................... 18

1.8.2. PCS Features..........................................................................................20

1.9. PCI Express Gen1/Gen2/Gen3 Hard IP................................................................... 21

1.10. Interlaken PCS Hard IP...................................................................................... 21

1.11. 10G Ethernet Hard IP........................................................................................ 22

1.12. External Memory and General Purpose I/O........................................................... 22

1.13. Adaptive Logic Module (ALM).............................................................................. 23

1.14. Core Clocking................................................................................................... 24

1.15. Fractional Synthesis PLLs and I/O PLLs.................................................................25

1.16. Internal Embedded Memory................................................................................25

1.17. Variable Precision DSP Block............................................................................... 25

1.18. Hard Processor System (HPS)............................................................................. 28

1.18.1. Key Features of the Intel Stratix 10 HPS...................................................29

1.19. Power Management........................................................................................... 32

1.20. Device Configuration and Secure Device Manager (SDM)......................................... 32

1.21. Device Security..................................................................................................34

1.22. Configuration via Protocol Using PCI Express..........................................................34

1.23. Partial and Dynamic Reconfiguration.................................................................... 35

1.24. Fast Forward Compile......................................................................................... 35

1.25. Single Event Upset (SEU) Error Detection and Correction........................................35

1.26. Document Revision History for the Intel Stratix 10 GX/SX Device Overview................36

Stratix 10 GX/SX Device Overview

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