Differential-to-LVDS Buffer/Divider
with Internal Termination
IDT8S89872I
Datasheet
Description
The IDT8S89872I is a high speed Differential-to-LVDS Buffer/Divider
with Internal Termination. The IDT8S89872I has a selectable ÷2, ÷4,
÷8, ÷16 output dividers. The clock input has internal termination
resistors allowing it to interface with several differential signal types
while minimizing the number of required external components.
The nRESET/nDISABLE asynchronously resets the QB output bank.
QA outputs are synchronously enabled or disabled on the next falling
edge of IN, or rising edge of nIN. Please refer to the timing diagram
for details.
The device is packaged in a small, 3 x 3 mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
•
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Three LVDS outputs
Frequency divide select options: ÷2, ÷4, ÷8, ÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz
Additive phase jitter: 0.15ps (typical)
Output skew: 30ps (maximum), QBx, nQBx outputs
Part-to-part skew: 250ps (maximum)
Propagation Delay: 530ps (typical)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Enable
FF
Pin Assignment
16 15 14 13
12 IN
11 V
T
10 V
REF_AC
9 nIN
5
QA
V
DD
GND
S0
S1
nRESET/
nDISABLE
QB0 1
nQB0
Enable
MUX
2
QB1 3
QA
nQA
nQB1 4
6
nQA
7
V
DD
8
nRESET/
nDISABLE
IN
R
IN
QB0
2, 4,
8, 16
nQB0
V
T
nIN
R
IN
IDT8S89872I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
NL Package
Top View
QB1
nQB1
V
REF_AC
S1
Decoder
S0
©2017 Integrated Device Technology, Inc.
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IDT8S89872I Datasheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 14
Name
QB0, nQB0
QB1, nQB1
QA, nQA
V
DD
nRESET/
nDISABLE
nIN
V
REF_AC
V
T
IN
GND
S1, S0
Output
Output
Output
Power
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply pins.
Output reset and enable/disable pin. When LOW, resets the divider select, and align
Bank A and Bank B edges. In addition, when LOW, Bank A and Bank B will be
disabled. Input threshold is V
DD
/2V. Includes a 37k
pullup resistor.
LVTTL/LVCMOS interface levels.
Inverting differential LVPECL clock input. R
IN
= 50
termination to V
T
.
Reference voltage for AC-coupled applications. Equal to V
DD
– 1.4V (approx.).
Maximum sink/source current is ±2mA.
Termination input. Leave pin floating.
Non-inverting LVPECL differential clock input. R
IN
= 50
termination to V
T
.
Power supply ground.
Pullup
Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.
Input threshold is V
DD
/2. 37k
pull-up resistor.
LVCMOS/LVTTL interface levels.
8
9
10
11
12
13
15, 16
Input
Input
Output
Input
Input
Power
Input
Pullup
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
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IDT8S89872I Datasheet
Function Tables
Table 3. Truth Table
Inputs
nRESET/nDISABLE
1 (default)
1
1
1
0
S1
0
0
1
1 (default)
X
S0
0
1
0
1 (default)
X
Bank A
Input Clock
Input Clock
Input Clock
Input Clock
QA = LOW, nQA = HIGH; NOTE 1
Outputs
Bank B
Input Clock ÷2
Input Clock ÷4
Input Clock ÷8
Input Clock ÷16
QBx = LOW, nQBx = HIGH; NOTE 2
NOTE 1: On the next negative transition of the input signal.
NOTE 2: Asynchronous reset/disable function.
Figure 1. nRESET/nDISABLE Timing Diagram
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IDT8S89872I Datasheet
Absolute Maximum Ratings
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
V
REF_AC
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
±2mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
75
Maximum
2.625
103
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
S[1:0],
nRESET/nDISABLE
S[1:0],
nRESET/nDISABLE
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
1.7
0
Typical
Maximum
V
DD
+ 0.3
0.7
10
Units
V
V
μA
μA
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IDT8S89872I Datasheet
Table 4C. Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing; NOTE 1
Differential Input Voltage Swing
Input Current; NOTE 2
Bias Voltage
IN, nIN
V
DD
- 1.49
V
DD
- 1.38
IN, nIN
IN, nIN
IN, nIN
Test Conditions
IN to V
T
Minimum
40
0.15
0
0.15
0.3
Typical
50
Maximum
60
V
DD
+ 0.3
V
IH
– 0.15
1.3
2.6
45
V
DD
- 1.28
Units
V
V
V
V
mA
V
NOTE 1: Refer to Parameter Measurement Information,
Input Voltage Swing
diagram.
NOTE 2: Guaranteed by design.
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OUT
V
OH
V
OL
V
OCM
V
OCM
Parameter
Output Voltage Swing
Output High Voltage
Output Low Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
Test Conditions
Minimum
350
1.3
0.8
1.07
Typical
455
Maximum
550
1.66
1.25
1.43
50
Units
mV
V
V
V
mV
©2017 Integrated Device Technology, Inc.
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November 29, 2017
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