TLP2261
Photocouplers
GaAℓAs Infrared LED & Photo IC
TLP2261
1. Applications
•
•
•
Factory Networking
High-Speed Digital Interfacing for Instrumentation and Control Devices
I/O Interface Boards
2. General
The Toshiba TLP2261 consists of a high-output GaAℓAs light-emitting diode coupled with a high-speed photo-
diode-transistor chip. It is housed in the SO8L package. It is housed in a thin SO8L package of 2.35 mm (max).
The TLP2261 guarantees isolation voltage 5000 Vrms and compliant with international safety standards for
reinforced insulation. It has two circuits built into a single SO8L package, which can reduce the mounting area.
This photocoupler guarantees operation at up to 125
and on supplies from 2.7 V to 5.5 V. Since TLP2261
guarantees 2 mA low supply current (I
DDL
/I
DDH
), and 1.6 mA (T
a
= 125
)
low threshold input current(I
FHL
), it
contributes to energy saving of devices. It can be driven directly from a microcomputer by a low input current.
The TLP2261 has an internal Faraday shield that provides a guaranteed common-mode transient immunity of
±20
kV/µs.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Inverter logic type (Totem pole output)
Package: SO8L
Operating temperature: -40 to 125
Supply voltage: 2.7 to 5.5 V
Data transfer rate: 15 MBd (typ.) (NRZ)
Threshold input current: 1.3 mA (max) (@T
a
= 105
)
: 1.6 mA (max) (@T
a
= 125
)
Supply current: 2 mA (max)
Common-mode transient immunity:
±20
kV/µs (min)
Isolation voltage: 5000 Vrms (min)
UL-approved: UL1577, File No.E67349
cUL-approved: CSA Component Acceptance Service No.5A File No.E67349
VDE-approved: EN60747-5-5, EN60065, EN60950-1, EN 62368-1 (Note 1)
CQC-approved: GB4943.1, GB8898 Japan Factory
(10) Safety standards
Note 1: When a VDE approved type is needed, please designate the Option (D4)
(D4).
Start of commercial production
©2016 Toshiba Corporation
1
2016-08
2016-08-31
Rev.2.0
TLP2261
4. Packaging and Pin Assignment
1: Anode 1
2: Cathode 1
3: Cathode 2
4: Anode 2
5: GND
6: V
O
2 (Output 2)
7: V
O
1 (Output 1)
8: V
DD
11-6B1A
5. Internal Circuit (Note)
Note:
A 0.1-µF bypass capacitor must be connected between pin 8 and pin 5.
©2016 Toshiba Corporation
2
2016-08-31
Rev.2.0
TLP2261
6. Principle of Operation
6.1. Truth Table
Input
H
L
LED1 (2)
ON
OFF
M1 (3)
OFF
ON
M2 (4)
ON
OFF
Output1 (2)
L
H
6.2. Mechanical Parameters
Characteristics
Creepage distances
Clearance
Internal isolation thickness
Min
8.0
8.0
0.4
Unit
mm
7. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
LED
Input forward current
Input forward current derating
Input forward current (pulsed)
Input forward current derating
(pulsed)
Peak transient input forward
current
Peak transient input forward
current derating
Input power dissipation
Input power dissipation
derating
Input reverse voltage
Detector Output current
Output voltage
Supply voltage
Output power dissipation
Output power dissipation
derating
Common Operating temperature
Storage temperature
Lead soldering temperature
Isolation voltage
(10 s)
(AC, 60 s, R.H.
≤
60 %)
(T
a
≥
110
)
(T
a
≥
110
)
(T
a
≥
110
)
(T
a
≥
110
)
(T
a
≥
110
)
Symbol
I
F
∆I
F
/∆T
a
I
FP
∆I
FP
/∆T
a
I
FPT
∆I
FPT
/∆T
a
P
D
∆P
D
/∆T
a
V
R
I
O
V
O
V
DD
P
O
∆P
O
/∆T
a
T
opr
T
stg
T
sol
BV
S
(Note 4)
(Note 1)
(Note 1)
Note
(Note 1)
(Note 1)
(Note 1),
(Note 2)
(Note 1)
(Note 1),
(Note 3)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Rating
10
-0.4
20
-0.8
1
-40
20
-0.8
5
10
6
6
40
-1.6
-40 to 125
-55 to 125
260
5000
Vrms
mW
mW/
Unit
mA
mA/
mA
mA/
A
mA/
mW
mW/
V
mA
V
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Each channel
Note 2: Pulse width (PW)
≤
1 ms, duty = 50 %
Note 3: Pulse width (PW)
≤
1
µs,
300 pps
Note 4: This device is considered as a two-terminal device: Pins 1, 2, 3 and 4 are shorted together, and pins 5, 6, 7
and 8 are shorted together.
Note:
©2016 Toshiba Corporation
3
2016-08-31
Rev.2.0
TLP2261
8. Recommended Operating Conditions (Note)
Characteristics
Input on-state current
Input off-state voltage
Supply voltage
Operating temperature
Symbol
I
F(ON)
V
F(OFF)
V
DD
T
opr
Note
(Note 1),
(Note 2)
(Note 1)
(Note 3)
(Note 3)
Min
2
0
2.7
-40
Typ.
3.3 / 5.0
Max
6
0.8
5.5
125
Unit
mA
V
The recommended operating conditions are given as a design guide necessary to obtain the intended
performance of the device. Each parameter is an independent value. When creating a system design using
this device, the electrical characteristics specified in this datasheet should also be considered.
Note: A ceramic capacitor (0.1
µF)
should be connected between pin 8 and pin 5 to stabilize the operation of a high-
gain linear amplifier. Otherwise, this photocoupler may not switch properly. The bypass capacitor should be
placed within 1 cm of each pin.
Note 1: Each channel
Note 2: The rise and fall times of the input on-current should be less than 0.5
µs.
Note 3: Denotes the operating range, not the recommended operating condition.
Note:
9. Electrical Characteristics (Note)
(Unless otherwise specified, T
a
= -40 to 125
, V
DD
= 2.7 to 5.5 V)
Characteristics
Input forward voltage
Input forward voltage
temperature coefficient
Input reverse current
Input capacitance
Low-level output voltage
High-level output voltage
Symbol
V
F
∆V
F
/∆T
a
I
R
C
t
V
OL
V
OH
Note
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Test
Circuit
Test Condition
I
F
= 2 mA, T
a
= 25
I
F
= 2 mA
V
R
= 5 V, T
a
= 25
V = 0 V, f = 1 MHz , T
a
= 25
Fig. I
F
= 2 mA, I
O
= 20
µA
12.1.1 I = 2 mA, I = 3.2 mA
F
O
Fig. V
F
= 0.8 V, I
O
= -20
µA,
12.1.2 V
DD
= 3.3 V
V
F
= 0.8 V, I
O
= -20
µA,
V
DD
= 5 V
V
F
= 0.8 V, I
O
= -3.2 mA,
V
DD
= 3.3 V
V
F
= 0.8 V, I
O
= -3.2 mA,
V
DD
= 5 V
Low-level supply current
High-level supply current
Threshold input current (H/L)
I
DDL
I
DDH
I
FHL
(Note 1)
Fig. I
F1
= I
F2
= 2 mA
12.1.3
Fig. I
F1
= I
F2
= 0 mA
12.1.4
I
O
= 3.2 mA, V
O
< 0.4 V,
T
a
= -40 to 105
I
O
= 3.2 mA, V
O
< 0.4 V,
T
a
= -40 to 125
Min
1.35
3.2
4.9
2.3
4.0
Typ.
1.50
-2.0
20
0.0016
0.12
3.29
4.99
3.15
4.87
1.3
1.3
0.5
0.5
Max
1.65
10
0.1
0.4
2
2
1.3
1.6
mA
Unit
V
mV/
µA
pF
V
Note: All typical values are at V
DD
= 5 V, T
a
= 25
,
unless otherwise noted.
Note 1: Each channel
©2016 Toshiba Corporation
4
2016-08-31
Rev.2.0
TLP2261
10. Isolation Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Total capacitance (input to output)
Isolation resistance
Isolation voltage
Symbol
C
S
R
S
BV
S
Note
Test Condition
Min
1
×
10
12
5000
Typ.
0.8
1
×
10
14
10000
10000
Max
Vdc
Unit
pF
Ω
Vrms
(Note 1) V = 0 V, f = 1 MHz
(Note 1) V = 500 V, R.H.
≤
60 %
(Note 1) AC, 60 s
AC, 1 s in oil
DC, 60 s in oil
Note 1: This device is considered as a two-terminal device: Pins 1, 2, 3 and 4 are shorted together, and pins 5, 6, 7
and 8 are shorted together.
11. Switching Characteristics (Note)
(Unless otherwise specified, T
a
= -40 to 125
, V
DD
= 2.7 to 5.5 V)
Characteristics
Propagation delay time (H/L)
Propagation delay time (L/H)
Pulse width distortion
Propagation delay skew
(device to device)
Propagation delay time (H/L)
Propagation delay time (L/H)
Pulse width distortion
Propagation delay skew
(device to device)
Fall time
Rise time
Common-mode transient
immunity at output high
Common-mode transient
immunity at output low
Symbol
t
pHL
t
pLH
|t
pHL
-t
pLH
|
t
psk
t
pHL
t
pLH
|t
pHL
-t
pLH
|
t
psk
t
f
t
r
CM
H
(Note 3)
(Note 1), (Note 2),
(Note 3)
(Note 1), (Note 3)
V
IN
= 0
→
5 V,
R
T
= 1.68 kΩ, C
L
= 15 pF
V
IN
= 5
→
0 V,
R
T
= 1.68 kΩ, C
L
= 15 pF
Fig. I
F
= 0 mA,
12.1.6 R
T
= 820
Ω
/ 1.68 kΩ,
V
CM
= 1000 V
p-p
, T
a
= 25
I
F
= 2 mA,
R
T
= 820
Ω
/ 1.68 kΩ,
V
CM
= 1000 V
p-p
, T
a
= 25
(Note 1), (Note 2),
(Note 3)
(Note 1), (Note 3)
V
IN
= 5 V, R
T
= 1.68 kΩ,
C
L
= 15 pF
Note
(Note 1), (Note 3)
Test
Circuit
Test Condition
Min
-30
-30
±20
Typ.
54
45
9
51
43
8
3
3
±45
Max
80
80
25
30
80
80
25
30
kV/µs
Unit
ns
Fig. V
IN
= 3.3 V, R
T
= 820
Ω,
12.1.5 C
L
= 15 pF
CM
L
±20
±45
Note: All typical values are at V
DD
= 5 V, T
a
= 25
,
unless otherwise noted.
Note: Each channel
Note 1: f = 5 MHz, duty = 50 %, input current t
r
= t
f
= less than 5 ns, C
L
is approximately 15 pF which includes probe
and stray wiring capacitance.
Note 2: The propagation delay skew, t
psk
, is equal to the magnitude of the worst-case difference in t
pHL
and/or t
pLH
that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc).
Note 3: R
T
= R
1
+ R
2
= 820
Ω
/ 1.68 kΩ
Recommendation input resistance conditions : R
1
= R
2
= 420
Ω
/ 840
Ω
©2016 Toshiba Corporation
5
2016-08-31
Rev.2.0
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