Data Sheet
FEATURES
0.6 GHz to 3.0 GHz, 0.5 dB LSB, 6-Bit,
Silicon Digital Step Attenuator
HMC8073
FUNCTIONAL BLOCK DIAGRAM
HMC8073
15
A2
14
SI
13
CLK
12
LE
LOGIC
CONTROL
11
GND
10
GND
6-BIT DSA
9
RFOUT
14678-001
Attenuation range: 0.5 dB LSB steps to 31.5 dB
Low insertion loss
1.1 dB to 1.0 GHz
1.5 dB to 2.0 GHz
Tight attenuation accuracy
Less than ±0.25 dB (plus 3% of attenuation state)
Low phase shift error: 4° phase shift to 1.0 GHz
Bidirectional use: 30 dBm high power handling
Internal dc block on the RFIN/RFOUT pins
High linearity
P1dB: 31 dBm typical
Input IP3: 52 dBm typical
Safe state transitions
Serial interface with TTL/CMOS
Up to 8 devices on a single data bus
Single-supply operation: 3.3 V to 5.0 V
ESD sensitivity rating: Class 1C (1 kV human body model)
16-lead, 3 mm × 3 mm LFCSP package: 9 mm
2
VDD
A0
GND
RFIN
1
2
3
4
16
A1
GND
6
GND
5
GND
7
Figure 1.
APPLICATIONS
Cellular infrastructure
Microwave radios
Very small aperture terminals
Test equipment and sensors
GENERAL DESCRIPTION
The HMC8073 is a 6-bit digital step attenuator (DSA),
operating from 0.6 GHz to 3.0 GHz, that features 31.5 dB of
attenuation range with 0.5 dB steps.
The HMC8073 is implemented in a silicon process, offering a
fast settling time, low power consumption, and high
electrostatic discharge (ESD) robustness. The device features
safe state transitions, allowing attenuation state changes without
overshooting, and is optimized for excellent step accuracy and
high power and high linearity over frequency and temperature
range. The radio frequency (RF) input and output are internally
matched to 50 Ω and do not require any external matching
components. The design is bidirectional, and the RF input and
output are interchangeable.
The external address feature of the HMC8073 allows users to
control up to eight DSAs using a single bus. The DSA has an
on-chip regulator that supports a wide supply operating range
from 3.3 V to 5.0 V with no performance change in electrical
characteristics. The HMC8073 incorporates a complementary
metal-oxide semiconductor (CMOS)- and transistor transitory
logic (TTL)- compatible interface that supports serial (3-wire)
control of the attenuator.
The HMC8073 comes in an RoHS compliant, compact,
3 mm × 3 mm LFCSP package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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GND
8
HMC8073
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications ............................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics..................................................................... 6
Typical Performance Characteristics ............................................. 7
Data Sheet
Insertion Loss, Return Loss, State Error, Normalized
Attenuation, Step Error, and Relative Phase ..............................7
Input Power Compression and Third-Order Intercept ............9
Theory of Operation ...................................................................... 10
Power-Up Sequence ................................................................... 10
RF Input and Output ................................................................. 10
Serial Control Interface ............................................................. 10
Attenuation State at Power-Up ................................................. 10
Applications Information .............................................................. 12
Evaluation PCB ........................................................................... 12
Packaging and Ordering Information ......................................... 13
Outline Dimensions ................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
4/2018—Revision A: Initial Version
Rev. A | Page 2 of 13
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
V
DD
= 5.0 V, T
A
= 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
INSERTION LOSS
Test Conditions/Comments
0.6 GHz to 1.0 GHz
1.0 GHz to 2.0 GHz
2.0 GHz to 3.0 GHz
0.6 GHz to 3.0 GHz
Delta between minimum and
maximum attenuation states
Between any successive attenuation
states
Referenced to insertion loss; all
attenuation states
All attenuation states
All attenuation states
0.6 GHz to 1.0 GHz
1.0 GHz to 2.0 GHz
2.0 GHz to 3.0 GHz
0.6 GHz to 1.0 GHz
1.0 GHz to 2.0 GHz
2.0 GHz to 3.0 GHz
10% to 90% of RF output
50% V
CTL
to 90% of RF output
All attenuation states
Min
0.6
Typ
1.1
1.5
2.2
31.5
0.5
−(0.25 + 3% of
attenuation state)
±0.4
14
12
9
4
14
38
65
260
28
31
52
0.3
0.3
Max
3.0
HMC8073
Unit
GHz
dB
dB
dB
dB
dB
ATTENUATION
Range
Step Size, LSB
Accuracy
Step Error
RETURN LOSS
RFIN, RFOUT
+(0.25 + 3% of
attenuation state)
dB
dB
dBm
dBm
dBm
Degrees
Degrees
Degrees
ns
ns
dBm
dBm
dBm
mA
mA
RELATIVE PHASE
SWITCHING CHARACTERISTICS
Rise and Fall Time (t
RISE
, t
FALL
)
On and Off Time (t
ON
, t
OFF
)
INPUT LINEARITY
0.1 dB Compression (P0.1dB)
1 dB Compression (P1dB)
Input Third-Order Intercept
(IP3)
SUPPLY CURRENT (I
DD
)
CONTROL VOLTAGE
THRESHOLD, V
CTL
Low, V
IL
High, V
IH
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage Range (V
DD
)
Digital Control Voltage
Range
Maximum RF Input Power
Case Temperature (T
CASE
)
Two-tone input power = 16 dBm/tone,
∆f = 1 MHz
V
DD
= 3.3 V
V
DD
= 5.0 V
For CLK, LE, SI, A0, A1, A2; <1 µA typical
V
DD
= 3.3 V
V
DD
= 5.0 V
V
DD
= 3.3 V
V
DD
= 5.0 V
0
0
2
2
0.8
0.8
3.3
5.0
V
V
V
V
For CLK, LE, SI, A0, A1, A2
Worst case at maximum attenuation
3.3
0
5.0
V
DD
30
+85
V
V
dBm
°C
−40
Rev. A | Page 3 of 13
HMC8073
TIMING SPECIFICATIONS
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
Description
CLK period
CLK high
CLK low
SI to CLK setup time
CLK to SI hold time
LE to CLK setup time
CLK to LE hold time
LE pulse width
Min
5
2.5
2.5
1.5
1.5
1.5
1.5
2.5
Typ
Max
Data Sheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Timing Diagram
A2 TO A0
SI
X
X
D0
D1
D2
D3
D4
A2 TO A0 EXTERNAL ADDRESS SETTING
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
X
NEW ADDRESS
NEW WORD
X
t
4
CLK
t
5
t
7
t
8
t
6
14678-024
t
1
LE
t
2
t
3
Figure 2. Serial Control Timing Diagram
Rev. A | Page 4 of 13
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
RF Input Power (T
CASE
= 85°C)
Digital Control Inputs (CLK, LE, SI, A0,
A1, A2)
Supply Voltage (V
DD
)
Continuous Power Dissipation (P
DISS
)
Temperature
Channel Temperature
Storage
Maximum Reflow Temperature
ESD Sensitivity
Human Body Model (HBM)
Rating
30 dBm
−0.3 V to V
DD
+ 0.4 V
5.4 V
0.999 W
140°C
−65°C to +150°C
260°C (MSL3 Rating)
1 kV (Class 1C)
HMC8073
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JC
is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 4. Thermal Resistance
Package Type
CP-16-38
θ
JC
55
Unit
°C/W
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 5 of 13
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