dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302
16-Bit Microcontrollers and Digital Signal Controllers with
High-Speed PWM, ADC and Comparators
Operating Conditions
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Advanced Analog Features (Continued)
• ADC module:
- 10-bit resolution with Successive Approximation
Register (SAR) converter (2 Msps) and three
Sample-and-Hold (S&H) circuits
- Up to 8 input channels grouped into four conversion
pairs, plus two inputs for monitoring voltage references
- Flexible and independent ADC trigger sources
- Dedicated Result register for each
analog channel
Core: 16-Bit dsPIC33F CPU
•
•
•
•
•
Code Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Clock Management
•
•
•
•
•
±2% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Timers/Output Compare/Input Capture
•
•
•
•
Two 16-Bit General Purpose Timers/Counters
Input Capture module
Output Compare module
Peripheral Pin Select (PPS) to allow Function Remap
Communication Interfaces
• UART module (10 Mbps):
- With support for LIN/J2602 protocols and IrDA
®
• 4-Wire SPI module
• I
2
C™ module (up to 1 Mbaud) with SMBus Support
• PPS to allow Function Remap
Power Management
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
2.0 mA/MHz Dynamic Current (typical)
135 µA I
PD
Current (typical)
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 1.04 ns PWM Resolution for Dead Time, Duty Cycle,
Phase and Frequency
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Input/Output
• Constant Current Source:
- Constant current generator (10 µA nominal)
• Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• External Interrupts on 16 I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned
• Class B Safety Library, IEC 60730
Advanced Analog Features
• Two High-Speed Comparators with Direct Connection to
the PWM module:
- Buffered/amplified output drive
- Independent 10-bit DAC for each comparator
- Rail-to-rail comparator operation
- DACOUT amplifier (1x, 1.8x)
- Selectable hysteresis
- Programmable output polarity
- Interrupt generation capability
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Two Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
2011-2012 Microchip Technology Inc.
DS75018C-page 1
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 PRODUCT
FAMILIES
The device names, pin counts, memory sizes and periph-
eral availability of each device are listed in
Table 1.
The
following pages show their pinout diagrams.
TABLE 1:
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES
Program Flash Memory (Kbytes)
Remappable Peripherals
Constant Current Source
ADC
Sample-and-Hold (S&H) Circuit
Analog-to-Digital Inputs
External Interrupts
(1)
Analog Comparator
Remappable Pins
Output Compare
Reference Clock
RAM (Bytes)
DAC Output
Input Capture
16-Bit Timer
PWM
(2)
UART
SARs
SPI
Device
dsPIC33FJ06GS001
18
20
6
256
8
2
0
0
0
0
2x2
2
3
0
0
0
1
1
2
6
PDIP,
13 SOIC
SSOP
PDIP,
13 SOIC
SSOP
SPDIP,
SOIC,
21 SSOP,
QFN-S
VTLA
SPDIP,
SOIC,
21 SSOP,
QFN-S
VTLA
SPDIP,
SOIC,
21 SSOP,
QFN-S
VTLA
dsPIC33FJ06GS101A
18
20
28
36
28
36
28
36
6
256
8
2
0
1
1
1
2x2
0
3
0
0
1
1
1
3
6
dsPIC33FJ06GS102A
6
256 16
2
0
1
1
1
2x2
0
3
0
0
1
1
1
3
6
dsPIC33FJ06GS202A
6
1K
16
2
1
1
1
1
2x2
2
3
1
0
1
1
1
3
6
dsPIC33FJ09GS302
9
1K
16
2
1
1
1
1
3x2
2
3
1
1
1
1
1
3
8
Note
1:
2:
INT0 is not remappable.
The PWM4 pair is remappable and only available on dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices.
DS75018C-page 2
2011-2012 Microchip Technology Inc.
Packages
I/O Pins
I
2
C™
Pins
FPGA/CPLD
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