74LV74D,118 datasheet, PDF - EEWORLD Datasheet

74LV74D,118: DescriptionFlip Flop D-Type Pos-Edge 2-Element Automotive 14-Pin SO T/R; File Size743KB，18 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com

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74LV74D,118 Overview

Flip Flop D-Type Pos-Edge 2-Element Automotive 14-Pin SO T/R

74LV74D,118 Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.39.00.01
Logic Family	LV
Logic Function	D-Type
Number of Channels per Chip	2
Number of Elements per Chip	2
Number of Element Inputs	1
Number of Element Outputs	1
Bus Hold	No
Set/Reset	Set/Reset
Polarity	Inverting/Non-Inverting
Triggering Type	Positive-Edge
Maximum Propagation Delay Time @ Maximum CL (ns)	70(Typ)@1.2V\|24(Typ)@2V\|18(Typ)@2.7V\|13(Typ)@3.3V\|9.5(Typ)@5V
Absolute Propagation Delay Time (ns)	58
Process Technology	CMOS
Input Signal Type	Single-Ended
Maximum Low Level Output Current (mA)	12
Maximum High Level Output Current (mA)	-12
Minimum Operating Supply Voltage (V)	1
Typical Operating Supply Voltage (V)	3.3
Maximum Operating Supply Voltage (V)	5.5
Maximum Quiescent Current (mA)	0.08
Propagation Delay Test Condition (pF)	50
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	125
Packaging	Tape and Reel
Supplier Package	SO
Pin Count	14
Mounting	Surface Mount
Package Height	1.45(Max)
Package Length	8.75(Max)
Package Width	4(Max)
PCB changed	14

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74LV74

Dual D-type flip-flop with set and reset; positive-edge trigger

Rev. 4 — 9 December 2015

Product data sheet

1. General description

The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD)

inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ

outputs.

The set and reset are asynchronous active LOW inputs that operate independently of the

clock input. Information on the data input is transferred to the nQ output on the

LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action

in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

2. Features and benefits



Wide supply voltage range from 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Direct interface with TTL levels (2.7 V to 3.6 V)

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Specified from

40 C

to +85

C

and from

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Temperature range

74LV74D

74LV74DB

74LV74PW

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

Name

SO14

SSOP14

Description

plastic shrink small outline package; 14 leads; body width

5.3 mm

Version

SOT337-1

SOT402-1

Type number Package

plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

TSSOP14 plastic thin shrink small outline package; 14 leads; body

width 4.4 mm

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