dsPIC33FJ16MC304T-I/ML datasheet, PDF

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dsPIC33FJ16MC304T-I/ML: DescriptionDigital Signal Processors and Controllers - DSP, DSC 16B DSC 44LD16KB Motor40 MIPS; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，331 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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dsPIC33FJ16MC304T-I/ML Overview

Digital Signal Processors and Controllers - DSP, DSC 16B DSC 44LD16KB Motor40 MIPS

dsPIC33FJ16MC304T-I/ML Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
Parts packaging code	QFN
package instruction	8 X 8 MM, LEAD FREE, PLASTIC, QFN-44
Contacts	44
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Factory Lead Time	19 weeks
Has ADC	YES
Address bus width
bit size	16
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width
Format	FLOATING POINT
JESD-30 code	S-PQCC-N44
JESD-609 code	e3
length	8 mm
Humidity sensitivity level	1
Number of I/O lines	35
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC44,.32SQ,25
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
RAM (number of words)	1024
ROM programmability	FLASH
Maximum seat height	1 mm
speed	40 MHz
Maximum slew rate	70 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	8 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304

16-bit Digital Signal Controllers (up to 32 KB Flash and

2 KB SRAM) with Motor Control and Advanced Analog

Operating Conditions

• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS

• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS

• Six analog inputs on 28-pin devices and up to

nine analog inputs on 44-pin devices

• Flexible and independent ADC trigger sources

Core: 16-bit dsPIC33F CPU

•

Code-efficient (C and Assembly) architecture

Two 40-bit wide accumulators

Single-cycle (MAC/MPY) with dual data fetch

Single-cycle mixed-sign MUL plus hardware divide

Timers/Output Compare/Input Capture

• Three 16-bit timers/counters. Can pair up two to

make one 32-bit.

• Two Output Capture modules configurable as

timers/counters

• Four Input Capture modules

• Peripheral Pin Select (PPS) to allow function

remap

Clock Management

•

2% internal oscillator

Programmable PLLs and oscillator clock sources

Fail-Safe Clock Monitor (FSCM)

Independent Watchdog Timer (WDT)

Fast wake-up and start-up

Communication Interfaces

One UART module (10 Mbps)

With support for LIN 2.0 protocols and IrDA

One 4-wire SPI module (15 Mbps)

One I

C™ module (up to 1 Mbaud) with SMBus

support

• PPS to allow function remap

•

Power Management

•

Low-power management modes (Sleep, Idle, Doze)

Integrated Power-on Reset and Brown-out Reset

1.35 mA/MHz dynamic current (typical)

μA

IPD current (typical)

Input/Output

• Sink/Source up to 10 mA (pin specific) for stan-

dard VOH/VOL, up to 16 mA (pin specific) for

non-standard VOH1

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• Up to 5 mA overvoltage clamp current

• External interrupts on all I/O pins

High-Speed PWM

•

Up to four PWM pairs with independent timing

Dead time for rising and falling edges

12.5 ns PWM resolution

PWM support for:

- DC/DC, AC/DC, Inverters, PFC, Lighting

- BLDC, PMSM, ACIM, SRM

• Programmable Fault inputs

• Flexible trigger configurations for ADC conversions

Qualification and Class B Support

• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)

• Class B Safety Library, IEC 60730

Advanced Analog Features

• ADC module:

- Configurable as 10-bit, 1.1 Msps with four

S&H or 12-bit, 500 ksps with one S&H

Debugger Development Support

•

In-circuit and in-application programming

Two program and two complex data breakpoints

IEEE 1149.2-compatible (JTAG) boundary scan

Trace and run-time watch

Packages

Type

SPDIP

SOIC

SSOP

0.65

10.2x5.3x1.75

QFN-S

0.65

6x6x0.9

QFN

0.65

8x8x0.9

TQFP

0.80

10x10x1

Pin Count

Contact Lead/Pitch

.100''

1.27

I/O Pins

Dimensions

1.365x.285x.135''

17.9xx7.50x2.05

Note:

All dimensions are in millimeters (mm) unless specified.

2007-2012 Microchip Technology Inc.

DS70283K-page 1

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