Operating Temperature Range .........................
-40°C to +125°C
Junction Temperature .......................................Internally
Limited
Storage Temperature Range ............................
-65°C to +150°C
Lead Temperature (Soldering, 10 sec)
............................
+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TQFN16
Junction-to-Ambient Thermal Resistance (θ
JA
) ..........35°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ..............2.7°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
PARAMETER
V
DD
SUPPLY
Supply Voltage
(V
DD
= +10V to +40V, V5 = +4.5V to +5.5V, VL = +2.5V to +5.5V, R
LIM
= 27kΩ to 220kΩ, T
A
= -40°C to +125°C, unless otherwise
noted. Typical values are at T
A
= +25°C and V
DD
= +24V, VL = +3.3V and V5 = +5V, R
LIM
= 50kΩ) (Note 2)
SYMBOL
CONDITIONS
Operating Conditions
Tolerant
HS mode, PP = low, IN = VL, DOI high
(no switching), no load, V5 = VL =
REGIN, V
DD
= 40V
PP mode, PP = high, 10kHz switching,
V5 = VL = REGIN, no load
DI_EN = VL, REGIN = 40V
V
DD
rising, V5 = VL
V
DD
falling, V5 = VL
V5 = 5V
V
DD
rising, V5 = 5V
V
DD
falling, V5 = 5V
V5 = 5V
41.5
40.5
8.5
8
MIN
10
0
0.6
0.85
0.13
9.1
8.6
0.5
43.5
42.2
1
45
44
TYP
MAX
40
60
0.95
1.4
0.3
9.7
9
V
V
V
V
V
V
mA
UNITS
V
V
V
VDD
I
VDD_ON_HS
Supply Current
I
VDD_ON_PP
I
VDD_ON_DI
Undervoltage-Lockout
Threshold
Undervoltage-Lockout
Hysteresis
V
DD
Overvoltage-Lockout
Threshold
V
DD
Overvoltage-Lockout
Hysteresis
VL Supply Voltage
VL Supply Current
VL POR Threshold
V
VDD_UV
V
VDD_UVHYST
V
VDD_OVLO
V
VDD_OVHYST
V
VL
I
VL
V
VL_POR
VL LOGIC INTERFACE SUPPLY
2.5
All logic inputs high or low, all outputs
unloaded
VL falling
1.12
10
1.27
5.5
25
1.52
V
µA
V
www.maximintegrated.com
Maxim Integrated │
2
MAX14914
High-Side Switch with Settable Current-Limiting,
Push-Pull Driver Option and Digital Input Configuration
Electrical Characteristics (continued)
(V
DD
= +10V to +40V, V5 = +4.5V to +5.5V, VL = +2.5V to +5.5V, R
LIM
= 27kΩ to 220kΩ, T
A
= -40°C to +125°C, unless otherwise
noted. Typical values are at T
A
= +25°C and V
DD
= +24V, VL = +3.3V and V5 = +5V, R
LIM
= 50kΩ) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
HS mode, REGIN = 40V, IN = VL, no
load on DOI, no load on V5
PP = high, REGIN = 40V, 10kHz
switching, no load on DOI, no load on V5
DI_EN=VL, REGIN = 40V
HS Mode, REGIN = V5, IN = VL, no load
on DOI
PP Mode, REGIN = V5,10kHz switching,
no load on DOI
DI Mode, DI_EN = high, REGIN =
V5
REGIN rising
6.75
0.45
V5 rising
3.8
0.3
0mA – 20mA external load
4.75
25
PP = X, IN = high, I
DOI
= 500mA
PP = high, IN = low, I
DOI
= 100mA
Relative to V
DD
, I
DOI
= 500mA,
V
VDD
< V
VDD_OVLO
Relative to GND, I
DOI
= 500mA,
V
VDD_OVLO
< V
VDD
<60V
V
DD
= 40V, PP = IN = low, DI_EN = low,
0V< V
DOI
< V
VDD
V
DD
= 60V, PP = IN = X, DI_EN = low,
0V < V
DOI
< V
VDD
R
LIM
= 220kΩ
R
LIM
= 27kΩ
(Note 3)
(Note 3)
-63
-4.5
-60
-150
-55
-2.9
120
240
1.2
-49
-1.5
60
µA
150
5.0
5.25
4.2
0.24
0.3
0.22
MIN
TYP
MAX
UNITS
5V SUPPLY/LINEAR REGULATOR
REGIN Current HS Mode
REGIN Current PP Mode
REGIN Current DI Mode
I
REGIN_ON_HS
I
REGIN_ON_PP
I
REGIN_ON_DI
I
V5HS
V5
Supply Current
I
V5PP
I
V5DI
REGIN Undervoltage-
Lockout Threshold
REGIN Undervoltage-
Lockout Hysteresis
V
REG_UV
V
REG_UVHYST
V
V5_UV
V
V5UV_UVHYST
V
5
I
V5_CL
R
DOI_ON_HS
V
DOI_LOW
0.3
0.35
0.5
0.6
0.5
0.4
0.5
0.4
7.6
mA
mA
mA
mA
mA
mA
V
V
V
V
V
mA
mΩ
V
V
V
V5
Undervoltage-Lockout
Threshold
V5
Undervoltage-Lockout
Hysteresis
V5
Output Voltage
V5
Current Limit
DRIVER OUTPUT (DOI)
HS On-Resistance
LS Output Low
DOI Clamp Voltage
V
DOI_CL
DOI Leakage
I
DOI_LK
OUTPUT DRIVER CURRENT LIMITING (DOI)
HS
Current-Limit Minimum
HS
Current-Limit Maximum
HS Current-Limit Offset Error
HS Current-Limit Gain Error
I
CLIM_HS_MIN
I
CLIM_HS_MA
X
I
CLIM_HS_OE
I
CLIM_HS_GE
135
1.3
-25
-20
196
1.6
255
1.9
+25
+20
mA
A
mA
%
www.maximintegrated.com
Maxim Integrated │
3
MAX14914
High-Side Switch with Settable Current-Limiting,
Push-Pull Driver Option and Digital Input Configuration
Electrical Characteristics (continued)
(V
DD
= +10V to +40V, V5 = +4.5V to +5.5V, VL = +2.5V to +5.5V, R
LIM
= 27kΩ to 220kΩ, T
A
= -40°C to +125°C, unless otherwise
noted. Typical values are at T
A
= +25°C and V
DD
= +24V, VL = +3.3V and V5 = +5V, R
LIM
= 50kΩ) (Note 2)
PARAMETER
CLIM Voltage
CLIM Short
Resistor
Threshold Value
CLIM Open
Resistor
Threshold Value
LS Current Limit
DIGITAL INPUT / DOI MONITOR
DO Monitor Threshold Voltage
DO Monitor Hysteresis
DI Threshold Voltage
DI Hysteresis
DI Current Sink Type 1, 3
V
TH_DO
V
HYS_DO
V
TH_DI
V
HYS_DI
I
DOI
DI_EN = low, DOI rising
DI_EN = low, DOI falling
DI_EN = low
DI_EN = high, DOI rising
DI_EN = high, DOI falling
DI_EN = high
DI_EN = high, PP = low, 0V< V
DOI
< 5V
DI_EN = high, PP = low, 8V< V
DOI
< 40V
V
DOI
< V
DD
DI_EN = high, PP = high, 0V < V
DOI
< 5V
DI_EN = high, PP = high, 8V < V
DOI
< 40V,
V
DOI
< V
DD
2.0
0
6.0
7.0
2.3
6.7
5.5
1.2
2.6
2.6
7.5
7.7
mA
mA
1.5
1.3
0.2
8
6.8
2.0
1.8
V
V
V
V
SYMBOL
V
CLIM
R
LIM_SHORT
R
LIM_OPEN
I
CLIM_LS
(Note 4)
(Note 5)
10
440
150
CONDITIONS
MIN
TYP
1.21
12.9
15
750
280
MAX
UNITS
V
kΩ
kΩ
mA
DI Current Sink Type 2
LOGIC (I/O)
Input Voltage High
Input Voltage Low
Input Threshold Hysteresis
Input Pulldown Resistor
Output Logic-Low
DOI_LVL
Tristate Leakage
FAULT
Tristate Leakage
OV_VDD Leakage
THERMAL PROTECTION
Driver Thermal-Shutdown
Temperature
Driver Thermal-Shutdown
Hysteresis
Chip Thermal Shutdown
Chip Thermal-Shutdown
Hysteresis
I
DOI
V
IH
V
IL
V
IHYST
R
I
V
OL
I
LEAK
I
LEAK
I
LEAK
All logic input pins
I
LOAD
= +5mA
GND < V
DOI_LVL
< VL
GND < V
FAULT
< V5
GND < V
OV_VDD
< V
DD
0.7 x V
VL
0.3 x V
VL
0.11 x V
VL
140
-1
-1
-1
200
275
0.33
+1
+1
+1
V
V
V
kΩ
V
µA
µA
µA
T
JSHDN
T
JSHDN_HYST
T
CSHDN
T
CSHDN_HYST
Junction temperature rising
170
15
°C
°C
°C
°C
Temperature rising
150
10
www.maximintegrated.com
Maxim Integrated │
4
MAX14914
High-Side Switch with Settable Current-Limiting,
Push-Pull Driver Option and Digital Input Configuration
Electrical Characteristics (continued)
(V
DD
= +10V to +40V, V5 = +4.5V to +5.5V, VL = +2.5V to +5.5V, R
LIM
= 27kΩ to 220kΩ, T
A
= -40°C to +125°C, unless otherwise
noted. Typical values are at T
A
= +25°C and V
DD
= +24V, VL = +3.3V and V5 = +5V, R
LIM
= 50kΩ) (Note 2)
PARAMETER
TIMING CHARACTERISTICS
OUTPUT DRIVER (DOI)
Output Propagation Delay
LH
t
PD_LH
PP = X, delay from IN to DOI rising by 1V,
R
L
= 5kΩ, C
L
= 100pF (Figure 1)
PP = low, delay between IN switching low
to DOI falling by 1V. R
L
= 5kΩ,
C
L
= 100pF, V
DD
= 24V (Figure 1)
PP = high, delay between IN switching
low to DOI falling by 1V. R
L
= 5kΩ,
C
L
= 100pF (Figure 1)
PP = X, 20% to 80% VDD, R
L
= 5kΩ,
C
L
= 100pF, (Figure 2)
PP=high, 80% to 20% VDD, VDD = 24V,
R
L
= 5kΩ, C
L
= 100pF (Figure 2)
PP=low, 80% to 20% VDD, VDD = 24V,
R
L
= 47Ω, C
L
= 100pF (Figure 2)
DI_EN = low, delay from DOI rising to 5V
to
DOI_LVL
low (Figure 3)
DI_EN = high, delay from DOI rising to 8V
to
DOI_LVL
low
DI_EN = low, delay from DOI falling to
3.5V to
DOI_LVL
high
DI_EN = high, delay from DOI falling to
5.5V to
DOI_LVL
high
0.4
1.5
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.6
1.5
µs
Output Propagation Delay
HL
t
PD_HL
0.6
0.9
0.65
1
1.5
2
2
µs
µs
DOI Output Rise Time
t
R
DOI Output Fall Time
t
F
PROPAGATION DELAY (DOI toDOI_LVL)
Propagation Delay LH
Propagation Delay LH DI
Propagation Delay HL
Propagation Delay HL DI
GLITCH REJECTION (IN)
Pulse Length of Rejected
Glitch
Glitch Filter Delay Time
OV_VDD Threshold
OVLO_VDD Debounce
Time
OVLO_VDD Output
Leakage
FAULT Output Leakage
Note 2:
Note 3:
Note 4:
Note 5:
t
FPL_GF
t
D_GF
V
TH_OV_VDD
TD
OVLO_VDD
I
LK_OV_VDD_
I
LK_FAULT
DI_EN = low, relative to V
DD
DI_EN = low
0 < I
OV
< VDD
0 < I
FAULT
< 5V
-1
-1
0
140
0.22
200
+1
+1
80
300
ns
ns
V
µs
µA
µA
t
PDL_LH
t
PDL_LH_DI
t
PDL_HL
t
PDL_HL_DI
2.7
1.1
0.9
0.9
8
5
µs
µs
µs
µs
FAULT DETECTION (OV_VDD, FAULT)
All units are production tested at T
A
= +25°C. Specification over temperature are guaranteed by characterization and design.
Specification is guaranteed by design; not production tested.
Lower resistor values than CLIM_SHORT act like a CLIM pin short to GND.
Higher resistor values than CLIM_OPEN act like a CLIM open circuit.
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