PCA9510AD,112 datasheet, PDF - EEWORLD Datasheet

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PCA9510AD,112: DescriptionBuffers and Line Drivers HOT SWAP I2C/SMBUS; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size136KB，25 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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PCA9510AD,112 Overview

Buffers and Line Drivers HOT SWAP I2C/SMBUS

PCA9510AD,112 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Manufacturer packaging code	SOT96-1
Reach Compliance Code	compliant
Interface integrated circuit type	INTERFACE CIRCUIT
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	4.9 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum slew rate	6 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	2.7 V
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm
Base Number Matches	1

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PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

Rev. 04 — 18 August 2009

Product data sheet

1. General description

The PCA9510A is a hot swappable I

C-bus and SMBus buffer that allows I/O card

insertion into a live backplane without corrupting the data and clock buses. Control

circuitry prevents the backplane from being connected to the card until a stop command or

bus idle occurs on the backplane without bus contention on the card. When the

connection is made, the PCA9510A provides bidirectional buffering, keeping the

backplane and card capacitances isolated.

The PCA9510A has no rise time accelerator circuitry to prevent interference when there

are multiple devices in the same system. The PCA9510A incorporates a digital ENABLE

input pin, which enables the device when asserted HIGH and forces the device into a Low

current mode when asserted LOW, and an open-drain READY output pin, which indicates

that the backplane and card sides are connected together (HIGH) or not (LOW).

During insertion, the PCA9510A SDAIN and SCLIN pins (inputs only) are precharged to

1 V to minimize the current required to charge the parasitic capacitance of the chip.

Remark:

The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow

them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in

parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A

cannot

connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side

or P82B96 Sx/y side.

2. Features

Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and

SCL corruption during live board insertion and removal from multipoint backplane

systems

Compatible with Standard-mode I

C-bus, Fast-mode I

C-bus, and SMBus standards

Active HIGH ENABLE input

Active HIGH READY open-drain output

High-impedance SDAn and SCLn pins for V

= 0 V

1 V precharge on SDAIN and SCLIN inputs

Supports clock stretching and multiple master arbitration and synchronization

Operating power supply voltage range: 2.7 V to 5.5 V

5 V tolerant I/Os

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO8, TSSOP8 (MSOP8)

NXP Semiconductors

PCA9510A

Hot swappable I

C-bus and SMBus bus buffer

8. Functional description

Refer to

Figure 1 “Block diagram of PCA9510A”.

8.1 Start-up

An undervoltage and initialization circuit holds the parts in a disconnected state which

presents high-impedance to all SDAn and SCLn pins during power-up. A LOW on the

ENABLE pin also forces the parts into the low current disconnected state when the I

essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is

powered and the ENABLE is taken from LOW to HIGH, it enters an initialization state

where the internal references are stabilized and the precharge circuit is enabled. At the

end of the initialization state the ‘Stop Bit And Bus Idle’ detect circuit is enabled. With the

ENABLE pin HIGH long enough to complete the initialization state (t

) and remaining

HIGH when all the SDAn and SCLn pins have been HIGH for the bus idle time or when all

pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is

connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry

is activated during the initialization and is deactivated when the connection is made. The

precharge circuitry pulls up the SDAIN and SCLIN input pins to 1 V through individual

100 kΩ nominal resistors. This precharges the pins to 1 V to minimize the worst case

disturbances that result from inserting a card into the backplane where the backplane and

the card are at opposite logic levels.

8.2 Connect circuitry

Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as

SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that

isolates the input capacitance from the output bus capacitance while communicating the

logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be

driven to a LOW by the part. The same is also true for the SCLn pins. Noise between

0.7V

and V

is generally ignored because a falling edge is only recognized when it

falls below 0.7V

with a slew rate of at least 1.25 V/µs. When a falling edge is seen on

one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small

voltage above the falling pin. The driver will pull the pin down at a slew rate determined by

the driver and the load initially, because it does not start until the ﬁrst falling pin is below

0.7V

. The ﬁrst falling pin may have a fast or slow slew rate, if it is faster than the

pull-down slew rate then the initial pull-down rate will continue. If the ﬁrst falling pin has a

slow slew rate then the second pin will be pulled down at its initial slew rate only until it is

just above the ﬁrst pin voltage then they will both continue down at the slew rate of the

ﬁrst.

Once both sides are LOW they will remain LOW until all the external drivers have stopped

driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV

by external drivers, which is the case for clock stretching and is typically the case for

acknowledge, and one side external driver stops driving that pin will rise until the internal

driver pulls it down to the offset voltage. When the last external driver stops driving a

LOW, that pin will rise up and settle out just above the other pin as both rise together with

a slew rate determined by the internal slew rate control and the RC time constant. As long

as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V for the

PCA9510A, the pull-down driver is turned off.

PCA9510A_4

Product data sheet

Rev. 04 — 18 August 2009

5 of 24

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