DATASHEET
ACS541MS
Radiation Hardened Octal Buffer/Line Driver Three-State
FN4085
Rev.0.00
January 1996
Features
• Devices QML Qualified in Accordance with MIL-PRF-
38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-96710 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/
Bit/Day (Typ)
• SEU LET Threshold>100 MEV-cm
2
/mg
• Dose Rate Upset>10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability>10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range-55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL
Logic
• DC Operating Voltage Range 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current
1A at VOL, VOH
• Fast Propagation Delay17ns (Max), 12ns (Typ)
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
OE1
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 VCC
19 OE2
18 Y0
17 Y1
16 Y2
15 Y3
14 Y4
13 Y5
12 Y6
11 Y7
GND 10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
OE1
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
OE2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Description
The Intersil ACS541MS is a Radiation Hardened Octal Buf-
fer/Line Driver, with three-state outputs. The output enable
pins OE1, OE2 control the Three-State outputs. If either
enable is high the output will be in a high impedance state.
For data output both enables must be low.
The ACS541MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
a radiation hardened, high-speed, CMOS/SOS Logic family.
The ACS541MS is supplied in a 20 lead Ceramic Flatpack
(K suffix) or a Ceramic Dual-In-Line package (D suffix).
Ordering Information
PART NUMBER
5962F9671001VRC
5962F9671001VXC
ACS541D/Sample
ACS541K/Sample
ACS541HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
FN4085 Rev.0.00
January 1996
Page 1 of 3
ACS541MS
Functional Diagram
A0
OE1
OE2
19
A1
3
1
GND
VCC
17
Y1
2
VCC
18
Y0
A2
4
GND
VCC
16
Y2
A3
5
GND
VCC
15
Y3
A4
6
GND
VCC
14
Y4
A5
7
GND
VCC
13
Y5
A6
8
GND
VCC
12
Y6
GND VCC
10
20
A7
9
GND
VCC
11
Y7
GND
TRUTH TABLE
INPUTS
OE1
L
L
H
X
OE2
L
L
X
H
An
H
L
X
X
OUTPUTS
Yn
H
L
Z
Z
NOTE: L = Low Logic Level, H = High Logic Level, Z = High Impedance
© Copyright Intersil Americas LLC 1999. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see
www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at
www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
FN4085 Rev.0.00
January 1996
Page 2 of 3
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