UM10541
NVT2008PW and NVT2010PW demo boards
Rev. 1 — 7 March 2012
User manual
Document information
Info
Keywords
Content
NVT, voltage translator, level translator, level shift, passive voltage
translator, passive level translator, passive level shift, I2C-bus, SMBus,
SPI, NVT2008, NVT2010
NXP Voltage Translators (NVT) are used in bidirectional signaling voltage
level translation applications for I/O buses with incompatible logic levels.
The NVT2008 and NVT2010 are eight- and ten-channel voltage
translators, operational from 1.0 V to 3.6 V at V
CC(A)
(low voltage side) and
1.8 V to 5.5 V at V
CC(B)
(high voltage side) without direction control for
open-drain or push-pull I/O devices.
Abstract
NXP Semiconductors
UM10541
NVT2008PW and NVT2010PW demo boards
Revision history
Rev
v.1
Date
20120307
Description
user manual; initial release
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10541
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
2 of 7
NXP Semiconductors
UM10541
NVT2008PW and NVT2010PW demo boards
1. Introduction
The NVT2008PW (OM13317) and NVT2010PW (OM13324) demo boards are designed
to let customers evaluate the NXP 8-channel and 10-channel bidirectional voltage level
translators. The demo boards interface between device I/Os operating at different voltage
levels. Since the NVT2008PW and NVT2010PW devices are passive devices, pull-up
resistors may be needed depending on the I/O interface type (totem pole or open-drain),
difference in translation voltage, and the translation direction (high-to-low voltage,
low-to-high voltage, or bidirectional). The NVT2008PW and NVT2010PW devices allow
translations between any voltages from 1.0 V to 5.5 V.
Please refer to NVT2008/NVT2010 data sheet (Ref.
1)
and application note
AN11127
(Ref.
2)
for more detailed information.
019aac713
019aac714
a. NVT2008PW (OM13317)
Fig 1.
Bidirectional voltage level translators demo boards
b. NVT2010PW (OM13324)
UM10541
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
3 of 7
NXP Semiconductors
UM10541
NVT2008PW and NVT2010PW demo boards
2. Hardware description
2.1 Schematic
The demo boards contain footprints for the NVT2008PW and NVT2010PW devices, the
jumpers, headers, and passive components are shared. The NVT2008PW and
NVT2010PW demo board schematic is shown in
Figure 2.
Pins 2 and 3 on J1 must be
shorted to enable the part. Pins 1 and 12 on J2 are power and GND for the low voltage
side. Pins 1 and 12 on J4 are power and GND for the high voltage side. All Bn I/O pins on
the right side have 10 kΩ pull-up resistors to VREFB and all An I/O pins on the left side
have 10 kΩ pull-up resistors to VREFA through jumper J3. A shunt must be installed at J3
if VREFB
−
VREFA < 1 V. If VREFB
−
VREFA
≥
1 V, then the J3 jumper should be open
and resistors R2 through R11 must be removed. If they are not removed, then a resistive
path exists between the A-side I/Os that can impact the efficiency and signal integrity of
the solution.
J1
low voltage
A-side
J2
1
2
3
4
5
6
7
8
9
10
11
12
VREFA
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
Jumper J3:
ON: if VREFB − VREFA < 1 V
OFF: if VREFB − VREFA ≥ 1 V
(R2 to R11 pull-up resistors
NVT2010PW
must be removed)
GND
EN
1
24
VREFA
VREFB
J3
2
23
A1
B1
3
22
A2
B2
4
21
A3
B3
5
20
A4
B4
6
19
A5
B5
7
18
A6
B6
8
17
A7
B7
9
16
A8
B8
10
15
A9
B9
11
14
A10
B10
12
13
2
1
BUS_A[1:10]
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
R10
R11
R7
R8
R9
Jumper J1:
2-3: switch enable
1-2: switch disable
open: switch enable control input to J1-2
high voltage
B-side
J4
1
2
3
R1
200 kΩ
C1
EN_VB
0.1 μF
VREFB
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
GND
U1
1
2
3
4
5
6
7
8
9
10
11
12
MA12-1
BUS_B[1:10]
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
R19
10 kΩ
R20
10 kΩ
R12
10 kΩ
R15
R16
R17
R18
R13
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
MA12-1
GND
NVT2008PW
GND
VREFA
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
U2
20
19
18
17
16
15
14
13
12
11
EN
VREFB
B1
B2
B3
B4
B5
B6
B7
B8
002aag943
Fig 2.
NVT2008PW and NVT2010PW demo board schematic
UM10541
All information provided in this document is subject to legal disclaimers.
User manual
Rev. 1 — 7 March 2012
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
R14
R21
R2
R3
R4
R5
R6
10 kΩ
© NXP B.V. 2012. All rights reserved.
4 of 7
NXP Semiconductors
UM10541
NVT2008PW and NVT2010PW demo boards
2.2 Jumper and header functions
The functions of the jumpers and headers on these demo boards are shown in
Table 1.
Table 1.
J1 (3-pin)
Header descriptions for NVT2008PW (OM13317) and NVT2010PW (OM13324) demo boards
Function
Device switch enable or disable
control
Low voltage VREFA, GND and
An I/O signal connect pins
Notes
Short pins 2 and 3 to enable the NVT2008PW or NVT2010PW
device (default). When pins 1 and 2 are shorted, the device is
disabled.
Pin 1 = VREFA: low voltage power.
Pin 12 = GND: low voltage ground.
A[1:8] are low voltage signals for NVT2008PW.
A[1:10] are low voltage signals for NVT2010PW.
J3 (3-pin)
Connects 10 kΩ pull-up resistors to
VREFA on low voltage side for
VREFB
−
VREFA < 1 V
application required
High voltage VREFB, GND and
Bn I/O signal connect pins
Short pins 1 and 2 to connect 10 kΩ pull-up resistors to VREFA
on low voltage side (default).
Remark:
Pins 1 and 2 must be open and 10 kΩ pull-up resistors
must be removed when VREFB
−
VREFA
≥
1 V.
Pin 1 = VREFB: high voltage power.
Pin 12 = GND: high voltage ground.
B[1:8] are high voltage signals for NVT2008PW.
B[1:10] are high voltage signals for NVT2010PW.
Jumper/header
J2 (12-pin)
J4 (12-pin)
3. References
[1]
NVT2008; NVT2010, “Bidirectional voltage-level translator for open-drain and
push-pull applications” —
Product data sheet; NXP Semiconductors;
www.nxp.com/documents/data_sheet/NVT2008_NVT2010.pdf
AN11127, “Bidirectional voltage level translators NVT20xx, PCA9306,
GTL2000, GTL2002, GTL2003, GTL2010” —
application note;
NXP Semiconductors;
www.nxp.com/documents/application_note/AN11127.pdf
[2]
UM10541
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
5 of 7
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