Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Chapter 2. Functional Description ........................................................................................................ 6
Receive MAC ............................................................................................................................................... 8
Transmit MAC ............................................................................................................................................ 10
Signal Descriptions ............................................................................................................................................. 11
Timing Specifications .......................................................................................................................................... 13
Transmit Interface ...................................................................................................................................... 13
Receive Interface ....................................................................................................................................... 13
Chapter 3. Parameter Settings ............................................................................................................ 14
Parameter Descriptions....................................................................................................................................... 14
Multicast Address Filter.............................................................................................................................. 14
Evaluation Generation Options .................................................................................................................. 15
Chapter 4. IP Core Generation............................................................................................................. 16
Licensing the IP Core.......................................................................................................................................... 16
Getting Started .................................................................................................................................................... 16
IPexpress-Created Files and Top Level Directory Structure............................................................................... 18
Instantiating the Core .......................................................................................................................................... 20
Running Functional Simulation ........................................................................................................................... 20
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 21
Hardware Evaluation........................................................................................................................................... 23
Enabling Hardware Evaluation in Diamond................................................................................................ 23
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 23
Updating/Regenerating the IP Core .................................................................................................................... 23
Regenerating an IP Core in Diamond ........................................................................................................ 23
Regenerating an IP Core in ispLEVER ...................................................................................................... 24
Chapter 5. Application Support........................................................................................................... 25
Reference Register Descriptions ........................................................................................................................ 25
Chapter 6. Support Resources ............................................................................................................ 45
Lattice Technical Support.................................................................................................................................... 45
Online Forums............................................................................................................................................ 45
Telephone Support Hotline ........................................................................................................................ 45
E-mail Support ........................................................................................................................................... 45
Local Support ............................................................................................................................................. 45
Internet ....................................................................................................................................................... 45
References.......................................................................................................................................................... 45
LatticeECP2/M ........................................................................................................................................... 45
LatticeECP3 ............................................................................................................................................... 45
LatticeSC/M................................................................................................................................................ 45
Revision History .................................................................................................................................................. 46
Appendix A. Resource Utilization ....................................................................................................... 47
LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 47
Ordering Part Number................................................................................................................................ 47
LatticeECP2M and LatticeECP2MS FPGAs ....................................................................................................... 47
Ordering Part Number................................................................................................................................ 47
LatticeECP3 FPGAs............................................................................................................................................ 48
Ordering Part Number................................................................................................................................ 48
LatticeSC/M FPGAs ............................................................................................................................................ 48
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG39_02.9, December 2010
2
10 Gb+ Ethernet MAC IP Core User’s Guide
Chapter 1:
Introduction
This document provides technical information about the Lattice 10 Gigabit Plus (10 Gb+) Ethernet Media Access
Controller (MAC) Intellectual Property (IP) core. The 10 Gb+ Ethernet MAC IP core comes with the following docu-
mentation and files:
• Protected netlist/database
• Behavioral RTL simulation model
• Source files for instantiating and evaluating the core
Quick Facts
Table 1-1
gives quick facts about the 10 Gb+ Ethernet MAC IP core for LattceECP2™, LatticeECP2M™,
LatticeECP3™, LatticeSC™, and LatticeSCM™ devices.
Table 1-1. 10 Gb+ Ethernet MAC IP Core Quick Facts
10 Gb+ Ethernet MAC IP Configuration
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Target Device
Resources
Utilization
Data Path Width
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
4050
4400
LatticeECP2
LFE2-35E-
7F672C
LFE2-35E-
7F672C
LatticeECP2M
LFE2M35E-
7F672C
LFSCM3GA2
5EP1-5F900C
LatticeECP3
LFE3-35EA-
8F672CES
LFE2M35E-
7F 672C
LatticeSC
LFSC3GA25E-
6F900C
LFSC3GA25E-
6F900C
LatticeSCM
LFSCM3GA25
EP1-6F900C
LFSCM3GA25
EP1-6F900C
64
4050
4
2800
Lattice Diamond™ 1.1 or ispLEVER
®
8.1SP1
Synopsys
®
Synplify™ Pro for D-2010.03L-SP1
Aldec
®
Active-HDL
®
8.2 Lattice Edition
Mentor Graphics
®
ModelSim
®
SE 6.3F
4400
4400
Features
• Compliant to IEEE 802.3-2005 standard, successfully passed University of New Hampshire InterOperability Lab-
oratory (UNH-IOL) 10GbE MAC hardware tests
1
• Supports standard 10Gbps Ethernet link layer data rate
• Supports rates up to 12Gbps by over-clocking
• 64-bit wide internal data path operating at 156.25MHz to 187.5MHz (187.5Mhz supported only on
LatticeSC/SCM)
• XGMII interface to the PHY layer (using IODDR external to the core)
• XAUI interface to the PHY layer (using PCS/SERDES external to the core)
• Simple FIFO interface with user's application
• Optional Multicast address filtering
1. Successfully passed all UNH-IOL Clause 4 (MAC), Clause 31 (Flow Control) and Clause 46 (Reconciliation Sublayer) testing.
IPUG39_02.9, December 2010
4
10 Gb+ Ethernet MAC IP Core User’s Guide
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