LAE5U-12F-6BG381E datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic IC> The FPGA - field programmable gate array (FPGA)> LAE5U-12F-6BG381E

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LAE5U-12F-6BG381E: DescriptionFPGA - Field Programmable Gate Array Auto Grade (AEC-Q100) ECP5, 12K LUTs, 1.1V; Categorysemiconductor Programmable logic IC The FPGA - field programmable gate array (FPGA); File Size1MB，98 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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LAE5U-12F-6BG381E Overview

FPGA - Field Programmable Gate Array Auto Grade (AEC-Q100) ECP5, 12K LUTs, 1.1V

LAE5U-12F-6BG381E Parametric

Parameter Name	Attribute value
Maker	Lattice
Product Category	FPGA - Field Programmable Gate Array
product	ECP5
Number of logic elements	12000
Number of logical array blocks - LAB	1500
Number of input/output terminals	197 I/O
Working power voltage	1.1 V
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 125 C
Installation style	SMD/SMT
Package/box	BGA-381
data rate	3.2 Gb/s
series	LAE5U
Distributed RAM	97 kbit
Embedded Block RAM - EBR	32
Maximum operating frequency	400 MHz
Factory packaging quantity	90
total memory	576 kbit

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ECP5™ Automotive Family

Data Sheet

FPGA-DS-02014 -1.1

June 2018

ECP5™ Automotive Family

Data Sheet

Contents

Acronyms in This Document .................................................................................................................................................7

1. General Description ......................................................................................................................................................8

1.1.

Features ...............................................................................................................................................................8

2. Architecture ................................................................................................................................................................10

2.1.

Overview ...........................................................................................................................................................10

2.2.

PFU Blocks .........................................................................................................................................................11

2.2.1. Slice ...............................................................................................................................................................12

2.2.2. Modes of Operation ......................................................................................................................................15

2.3.

Routing ..............................................................................................................................................................16

2.4.

Clocking Structure .............................................................................................................................................16

2.5.

sysCLOCK PLL .....................................................................................................................................................16

2.6.

Clock Distribution Network ...............................................................................................................................18

2.7.

Primary Clocks ...................................................................................................................................................18

2.8.

Dynamic Clock Control ......................................................................................................................................19

2.9.

Dynamic Clock Select.........................................................................................................................................19

2.10. Edge Clock .........................................................................................................................................................19

2.11. Clock Dividers ....................................................................................................................................................20

2.12. DDRDLL ..............................................................................................................................................................21

2.13. sysMEM Memory ..............................................................................................................................................22

2.13.1.

sysMEM Memory Block ............................................................................................................................22

2.13.2.

Bus Size Matching .....................................................................................................................................23

2.13.3.

RAM Initialization and ROM Operation ....................................................................................................23

2.13.4.

Memory Cascading ...................................................................................................................................23

2.13.5.

Single, Dual and Pseudo-Dual Port Modes ...............................................................................................23

2.13.6.

Memory Core Reset ..................................................................................................................................24

2.14. sysDSP™ Slice ....................................................................................................................................................25

2.14.1.

sysDSP Slice Approach Compared to General DSP ...................................................................................25

2.15. ECP5 Automotive sysDSP Slice Architecture Features ......................................................................................26

2.16. Programmable I/O Cells ....................................................................................................................................29

2.17. PIO .....................................................................................................................................................................31

2.17.1.

Input Register Block ..................................................................................................................................31

2.17.2.

Output Register Block ...............................................................................................................................32

2.18. Tri-state Register Block......................................................................................................................................33

2.19. DDR Memory Support .......................................................................................................................................34

2.19.1.

DQS Grouping for DDR Memory ...............................................................................................................34

2.19.2.

DLL Calibrated DQS Delay and Control Block (DQSBUF) ...........................................................................35

2.20. sysI/O Buffer ......................................................................................................................................................37

2.20.1.

sysI/O Buffer Banks...................................................................................................................................37

2.20.2.

Typical sysI/O I/O Behavior during Power-up...........................................................................................38

2.20.3.

Supported sysI/O Standards .....................................................................................................................38

2.20.4.

On-Chip Programmable Termination .......................................................................................................39

2.20.5.

Hot Socketing............................................................................................................................................39

2.21. SERDES and Physical Coding Sublayer ...............................................................................................................40

2.21.1.

SERDES Block ............................................................................................................................................41

2.21.2.

PCS ............................................................................................................................................................42

2.21.3.

SERDES Client Interface Bus .....................................................................................................................42

2.22. Flexible Dual SERDES Architecture ....................................................................................................................42

2.23. IEEE 1149.1-Compliant Boundary Scan Testability ............................................................................................43

2.24. Device Configuration .........................................................................................................................................43

2.24.1.

Enhanced Configuration Options..............................................................................................................43

2.24.2.

Single Event Upset (SEU) Support.............................................................................................................44

2.24.3.

On-Chip Oscillator.....................................................................................................................................44

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02014-1.1

ECP5™ Automotive Family

Data Sheet

2.25. Density Shifting ................................................................................................................................................. 45

3. DC and Switching Characteristics ............................................................................................................................... 46

3.1.

Absolute Maximum Ratings .............................................................................................................................. 46

3.2.

Recommended Operating Conditions ............................................................................................................... 46

3.3.

Power Supply Ramp Rates ................................................................................................................................ 47

3.4.

Power-On-Reset Voltage Levels ........................................................................................................................ 47

3.5.

Power up Sequence .......................................................................................................................................... 47

3.6.

Hot Socketing Specifications ............................................................................................................................. 47

3.7.

Hot Socketing Requirements............................................................................................................................. 48

3.8.

ESD Performance .............................................................................................................................................. 48

3.9.

DC Electrical Characteristics .............................................................................................................................. 48

3.10. Standby ECP5 Automotive Supply Current ....................................................................................................... 49

3.11. SERDES Power Supply Requirements ................................................................................................................ 50

3.12. sysI/O Recommended Operating Conditions .................................................................................................... 51

3.13. sysI/O Single-Ended DC Electrical Characteristics ............................................................................................. 52

3.14. sysI/O Differential Electrical Characteristics ..................................................................................................... 53

3.14.1.

LVDS.......................................................................................................................................................... 53

3.14.2.

SSTLD ........................................................................................................................................................ 53

3.14.3.

LVCMOS33D ............................................................................................................................................. 53

3.14.4.

LVDS25E .................................................................................................................................................... 54

3.14.5.

BLVDS25 ................................................................................................................................................... 55

3.14.6.

LVPECL33 .................................................................................................................................................. 56

3.14.7.

MLVDS25 .................................................................................................................................................. 57

3.14.8.

SLVS .......................................................................................................................................................... 58

3.15. Typical Building Block Function Performance ................................................................................................... 59

3.16. Derating Timing Tables...................................................................................................................................... 60

3.17. ECP5 Automotive Maximum I/O Buffer Speed ................................................................................................. 61

3.18. ECP5 Automotive External Switching Characteristics ....................................................................................... 62

3.19. sysCLOCK PLL Timing ......................................................................................................................................... 69

3.20. SERDES High-Speed Data Transmitter ............................................................................................................... 70

3.21. SERDES/PCS Block Latency ................................................................................................................................ 71

3.22. SERDES High-Speed Data Receiver .................................................................................................................... 72

3.23. Input Data Jitter Tolerance................................................................................................................................ 72

3.24. SERDES External Reference Clock ..................................................................................................................... 73

3.25. PCI Express Electrical and Timing Characteristics ............................................................................................. 74

3.25.1.

2.5 Gb/s PCIe AC and DC Characteristics .................................................................................................. 74

3.26. CPRI LV2 E.48 Electrical and Timing Characteristics – Preliminary ................................................................... 75

3.27. XAUI/CPRI LV E.30 Electrical and Timing Characteristics .................................................................................. 76

3.27.1.

AC and DC Characteristics ........................................................................................................................ 76

3.28. CPRI LV E.24 Electrical and Timing Characteristics ............................................................................................ 76

3.28.1.

AC and DC Characteristics ........................................................................................................................ 76

3.29. Gigabit Ethernet/SGMII/CPRI LV E.12 Electrical and Timing Characteristics .................................................... 77

3.29.1.

AC and DC Characteristics ........................................................................................................................ 77

3.30. SMPTE SD/HD-SDI/3G-SDI (Serial Digital Interface) Electrical and Timing Characteristics ............................... 78

3.30.1.

AC and DC Characteristics ........................................................................................................................ 78

3.31. ECP5 Automotive sysCONFIG Port Timing Specifications ................................................................................. 79

3.32. JTAG Port Timing Specifications ........................................................................................................................ 84

3.33. Switching Test Conditions ................................................................................................................................. 85

4. Pinout Information ..................................................................................................................................................... 87

4.1.

Signal Descriptions ............................................................................................................................................ 87

4.2.

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ........................................................ 90

4.3.

Pin Information Summary ................................................................................................................................. 91

4.3.1. LAE5UM ........................................................................................................................................................ 91

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02014-1.1

ECP5™ Automotive Family

Data Sheet

4.3.2. LAE5U ............................................................................................................................................................92

5. Ordering Information ..................................................................................................................................................94

5.1.

ECP5 Automotive Part Number Description .....................................................................................................94

5.2.

Ordering Part Numbers .....................................................................................................................................94

5.2.1. Automotive ...................................................................................................................................................94

Supplemental Information ..................................................................................................................................................95

Revision History ..................................................................................................................................................................96

Figures

Figure 2.1. Simplified Block Diagram of LAE5UM-45 Device (Top Level) ............................................................................11

Figure 2.2. PFU Diagram .....................................................................................................................................................11

Figure 2.3. Slice Diagram ....................................................................................................................................................13

Figure 2.4. Connectivity Supporting LUT5, LUT6, LUT7, and LUT8 .....................................................................................14

Figure 2.5. General Purpose PLL Diagram ...........................................................................................................................17

Figure 2.6. LAE5UM-45 Clocking .........................................................................................................................................18

Figure 2.7. DCS Waveforms ................................................................................................................................................19

Figure 2.8. Edge Clock Sources per Bank ............................................................................................................................20

Figure 2.9. ECP5 Automotive Clock Divider Sources ...........................................................................................................20

Figure 2.10. DDRDLL Functional Diagram ...........................................................................................................................21

Figure 2.11. ECP5 Automotive DLL Top Level View for LAE-45 ...........................................................................................22

Figure 2.12. Memory Core Reset ........................................................................................................................................24

Figure 2.13. Comparison of General DSP and ECP5 Automotive Approaches ....................................................................25

Figure 2.14. Simplified sysDSP Slice Block Diagram ............................................................................................................27

Figure 2.15. Detailed sysDSP Slice Diagram ........................................................................................................................28

Figure 2.16. Group of Four Programmable I/O Cells on Left/Right Side .............................................................................30

Figure 2.17. Input Register Block for PIO on Top Side of the Device ..................................................................................31

Figure 2.18. Input Register Block for PIO on Left or Right Side of the Device ....................................................................31

Figure 2.19. Output Register Block on Top Side .................................................................................................................32

Figure 2.20. Output Register Block on Left or Right Side ....................................................................................................33

Figure 2.21. Tri-state Register Block on Top Side ...............................................................................................................33

Figure 2.22. Tri-state Register Block on Left or Right Side ..................................................................................................34

Figure 2.23. DQS Grouping on the Left and Right Edges ....................................................................................................35

Figure 2.24. DQS Control and Delay Block (DQSBUF) .........................................................................................................36

Figure 2.25. ECP5 Automotive Device Family Banks ...........................................................................................................37

Figure 2.26. On-chip Termination .......................................................................................................................................39

Figure 2.27. SERDES/PCS Duals (LAE5UM-45) ....................................................................................................................40

Figure 2.28. Simplified Channel Block Diagram for SERDES/PCS Block ..............................................................................41

Figure 3.1. LVDS25E Output Termination Example ............................................................................................................54

Figure 3.2. BLVDS25 Multi-point Output Example ..............................................................................................................55

Figure 3.3. Differential LVPECL33 .......................................................................................................................................56

Figure 3.4. MLVDS25 (Multipoint Low Voltage Differential Signaling) ...............................................................................57

Figure 3.5. SLVS Interface ...................................................................................................................................................58

Figure 3.6. Receiver RX.CLK. Centered Waveforms ............................................................................................................66

Figure 3.7. Receiver RX.CLK. Aligned and DDR Memory Input Waveforms ........................................................................66

Figure 3.8. Transmit TX.CLK. Centered and DDR Memory Output Waveforms ..................................................................66

Figure 3.9. Transmit TX.CLK. Aligned Waveforms ...............................................................................................................67

Figure 3.10. DDRX71 Video Timing Waveforms ..................................................................................................................67

Figure 3.11. Receiver DDRX71_RX Waveforms ...................................................................................................................68

Figure 3.12. Transmitter DDRX71_TX Waveforms ..............................................................................................................68

Figure 3.13. Transmitter and Receiver Latency Block Diagram ..........................................................................................71

Figure 3.14. SERDES External Reference Clock Waveforms ................................................................................................73

Figure 3.15. sysCONFIG Parallel Port Read Cycle ................................................................................................................80

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02014-1.1

ECP5™ Automotive Family

Data Sheet

Figure 3.16. sysCONFIG Parallel Port Write Cycle............................................................................................................... 81

Figure 3.17. sysCONFIG Slave Serial Port Timing ................................................................................................................ 81

Figure 3.18. Power-On-Reset (POR) Timing ........................................................................................................................ 82

Figure 3.19. sysCONFIG Port Timing ................................................................................................................................... 82

Figure 3.20. Configuration from PROGRAMN Timing ......................................................................................................... 83

Figure 3.21. Wake-Up Timing ............................................................................................................................................. 83

Figure 3.22. Master SPI Configuration Waveforms ............................................................................................................ 84

Figure 3.23. JTAG Port Timing Waveforms ......................................................................................................................... 85

Figure 3.24. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................... 85

Tables

Table 1.1. ECP5 Automotive Family Selection Guide ............................................................................................................ 9

Table 2.1. Resources and Modes Available per Slice .......................................................................................................... 12

Table 2.2. Slice Signal Descriptions ..................................................................................................................................... 14

Table 2.3. Number of Slices Required to Implement Distributed RAM .............................................................................. 15

Table 2.4. PLL Blocks Signal Descriptions............................................................................................................................ 17

Table 2.5. DDRDLL Ports List ............................................................................................................................................... 21

Table 2.6. sysMEM Block Configurations ............................................................................................................................ 23

Table 2.7. Maximum Number of Elements in a Slice .......................................................................................................... 29

Table 2.8. Input Block Port ................................................................................................................................................. 32

Table 2.9. Output Block Port Description ........................................................................................................................... 33

Table 2.10. Tri-state Block Port .......................................................................................................................................... 34

Table 2.11. DQSBUF Port Description ................................................................................................................................. 36

Table 2.12. On-Chip Termination Options for Input Modes ............................................................................................... 39

Table 2.13. LAE5UM SERDES Standard Support ................................................................................................................. 41

Table 2.14. Available SERDES Duals per LAE5UM Device ................................................................................................... 41

Table 2.15. LAE5UM Mixed Protocol Support .................................................................................................................... 42

Table 2.16. Selectable Master Clock (MCLK) Frequencies during Configuration (Nominal) ............................................... 44

Table 3.1. Absolute Maximum Ratings ............................................................................................................................... 46

Table 3.2. Recommended Operating Conditions ................................................................................................................ 46

Table 3.3. Power Supply Ramp Rates ................................................................................................................................. 47

Table 3.4. Power-On-Reset Voltage Levels ......................................................................................................................... 47

Table 3.5. Hot Socketing Specifications .............................................................................................................................. 47

Table 3.6. Hot Socketing Requirements ............................................................................................................................. 48

Table 3.7. DC Electrical Characteristics ............................................................................................................................... 48

Table 3.8. Standby ECP5 Automotive Supply Current ........................................................................................................ 49

Table 3.9. ECP5UM Automotive ......................................................................................................................................... 50

Table 3.10. sysI/O Recommended Operating Conditions ................................................................................................... 51

Table 3.11. LVDS ................................................................................................................................................................. 53

Table 3.12. LVDS25E DC Conditions.................................................................................................................................... 54

Table 3.13. BLVDS25 DC Conditions ................................................................................................................................... 55

Table 3.14. LVPECL33 DC Conditions .................................................................................................................................. 56

Table 3.15. MLVDS25 DC Conditions .................................................................................................................................. 57

Table 3.16. Input to SLVS .................................................................................................................................................... 58

Table 3.17. Pin-to-Pin Performance.................................................................................................................................... 59

Table 3.18. Register-to-Register Performance ................................................................................................................... 60

Table 3.19. ECP5 Automotive Maximum I/O Buffer Speed ................................................................................................ 61

Table 3.20. ECP5 Automotive External Switching Characteristics ...................................................................................... 62

Table 3.21. sysCLOCK PLL Timing ........................................................................................................................................ 69

Table 3.22. Serial Output Timing and Levels ...................................................................................................................... 70

Table 3.23. Channel Output Jitter ....................................................................................................................................... 70

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02014-1.1

LAE5U-12F-6BG381E Related Products

	LAE5U-12F-6BG381E	LAE5UM-45F-6BG381E
Description	FPGA - Field Programmable Gate Array Auto Grade (AEC-Q100) ECP5, 12K LUTs, 1.1V	FPGA - Field Programmable Gate Array Auto Grade (AEC-Q100) ECP5, 43.8K LUTs, 1.1V, SERDES
Maker	Lattice	Lattice
Product Category	FPGA - Field Programmable Gate Array	FPGA - Field Programmable Gate Array
product	ECP5	ECP5
Number of logic elements	12000	44000
Number of logical array blocks - LAB	1500	5500
Number of input/output terminals	197 I/O	203 I/O
Working power voltage	1.1 V	1.1 V
Minimum operating temperature	- 40 C	- 40 C
Maximum operating temperature	+ 125 C	+ 125 C
Installation style	SMD/SMT	SMD/SMT
Package/box	BGA-381	BGA-381
series	LAE5U	LAE5UM
Distributed RAM	97 kbit	351 kbit
Embedded Block RAM - EBR	32	108
Maximum operating frequency	400 MHz	400 MHz
Factory packaging quantity	90	90
total memory	576 kbit	1944 kbit

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