X5329S8IZ-2.7A datasheet, PDF - EEWORLD Datasheet

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X5329S8IZ-2.7A: DescriptionMonitoring circuit CPU SUP 32K SPI EE RST HI 2 7-3 6V IND; CategoryPower/power management The power supply circuit; File Size331KB，21 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/; Environmental Compliance

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X5329S8IZ-2.7A Overview

Monitoring circuit CPU SUP 32K SPI EE RST HI 2 7-3 6V IND

X5329S8IZ-2.7A Parametric

Parameter Name	Attribute value
Brand Name	Intersil
Is it Rohs certified?	conform to
Maker	Renesas Electronics Corporation
Parts packaging code	SOIC
package instruction	SOP,
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	WATCHDOG TIMER, POWER-ON RESET CONTROL, SUPPLY VOLTAGE SUPERVISION
Adjustable threshold	YES
Analog Integrated Circuits - Other Types	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 code	R-PDSO-G8
JESD-609 code	e3
length	4.9 mm
Humidity sensitivity level	1
Number of channels	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3.9 mm

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X5328, X5329

(Replaces X25328, X25329)

Data Sheet

October 17, 2005

FN8132.1

CPU Supervisor with 32Kbit SPI EEPROM

FEATURES

• Low V

detection and reset assertion

—Five standard reset threshold voltages

—Re-program low V

reset threshold voltage

using special programming sequence

—Reset signal valid to V

= 1V

• Long battery life with low power consumption

—<1µA max standby current

—<400µA max active current during read

• 32Kbits of EEPROM

• Built-in inadvertent write protection

—Power-up/power-down protection circuitry

—Protect 0, 1/4, 1/2 or all of EEPROM array with

Block Lock

™

protection

—In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

—32-byte page write mode

—Self-timed write cycle

—5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply

operation

• Available packages

—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-free plus anneal available (RoHS compliant)

BLOCK DIAGRAM

SCK

Data

Command

Decode &

Control

Logic

DESCRIPTION

These devices combine three popular functions, Power-

on Reset Control, Supply Voltage Supervision, and Block

Lock Protect Serial EEPROM Memory in one package.

This combination lowers system cost, reduces board

space requirements, and increases reliability.

Applying power to the device activates the power-on

reset circuit which holds RESET/RESET active for a

period of time. This allows the power supply and oscilla-

tor to stabilize before the processor can execute code.

The device’s low V

detection circuitry protects the

user’s system from low voltage conditions by holding

RESET/RESET active when V

falls below a mini-

mum V

trip point. RESET/RESET remains asserted

until V

returns to proper operating level and stabi-

lizes. Five industry standard V

TRIP

thresholds are

available, however, Intersil’s unique circuits allow the

threshold to be reprogrammed to meet custom

requirements or to fine-tune the threshold in applica-

tions requiring higher precision.

Protect Logic

Status

EEPROM Array

8Kbits

16Kbits

Reset

Timebase

RESET/RESET

TRIP

Power-on and

Low Voltage

Reset

Generation

X5328 = RESET

X5329 = RESET

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X5329S8IZ-2.7A Related Products

	X5329S8IZ-2.7A	X5328PZ-2.7
Description	Monitoring circuit CPU SUP 32K SPI EE RST HI 2 7-3 6V IND	Monitoring circuit CPU SUP 32K SPI EE RST LW 2 7-5 5V 2
Brand Name	Intersil	Intersil
Is it Rohs certified?	conform to	conform to
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	SOIC	PDIP, SOIC
package instruction	SOP,	DIP,
Contacts	8	8, 8
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Other features	WATCHDOG TIMER, POWER-ON RESET CONTROL, SUPPLY VOLTAGE SUPERVISION	WATCHDOG TIMER, POWER-ON RESET CONTROL, SUPPLY VOLTAGE SUPERVISION
Adjustable threshold	YES	YES
Analog Integrated Circuits - Other Types	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 code	R-PDSO-G8	R-PDIP-T8
JESD-609 code	e3	e3
length	4.9 mm	9.585 mm
Number of channels	1	1
Number of functions	1	1
Number of terminals	8	8
Maximum operating temperature	85 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	DIP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	IN-LINE
Peak Reflow Temperature (Celsius)	260	NOT APPLICABLE
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	5.33 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	NO
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn)
Terminal form	GULL WING	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	40	NOT APPLICABLE
width	3.9 mm	7.62 mm

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