AS4C8M32MD2A-25BCN
8M x 32 Mobile LPDDR2 Synchronous DRAM (SDRAM)
Advance (Rev. 1.0,
Jun.
/2018)
Features
Fast clock rate: 400 MHz
Differential Clock inputs CK/CK#
JEDEC standard Compliant
Four-bit prefetch DDR architecture
Four internal banks, 2M x 32-bit for each bank
Double data rate architecture for command, address
and data Bus
Bidirectional/differential data strobe per byte of data
DQS/DQS#
Programmable Mode Registers
- READ and WRITE latencies (RL/WL)
- Burst length: 4, 8, or 16
- PASR (Partial Array Self Refresh)
Auto TCSR
(Temperature Compensated Self Refresh)
Auto Refresh and Self Refresh
Deep power-down
4096 refresh cycles / 32ms
Power supplies:
- V
DD1
= 1.8V (1.7V~1.95V)
- V
DD2
= 1.2V (1.14V~1.3V)
- V
DDCA
/V
DDQ
= 1.2V (1.14V~1.3V)
Interface: HSUL_12
Operating Temperature: T
C
= -25 ~ 85C
Package: 134-ball 10 x 11.5 x 1.0mm (max) FBGA
- Pb Free and Halogen Free
Overview
The
AS4C8M32MD2A
LPDDR2 SDRAM is a
high-speed
CMOS,
dynamic
random-access
memory containing 268,435,456 bits. It is internally
configured as a 4 banks of 2,097,152 words by 32
bits memory device. The devices use double data
rate architecture on the command/address (CA) bus
to reduce the number of input pins in the system. The
10-bit CA bus contains command, address, and
Bank/Row Buffer information. Each command uses
one clock cycle, during which command information
is transferred on both the positive and negative
edge of the clock. LPDDR2 also use double data
rate architecture on the DQ pins to achieve high
speed
operation.
The
double data
rate
architecture
is
essentially
a
4n
prefetch
architecture with an interface designed to transfer
two data bits per DQ every clock cycle at the I/O
pins. A single read or write access for the
LPDDR2 effectively consists of a single 4n-bit wide,
one clock cycle data transfer at the internal SDRAM/
NVM core and four corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins. Read
and write accesses to the LPDDR2 are burst
oriented; accesses start at a selected location
and continue for a programmed number of
locations in a programmed sequence.
Table 1. Ordering Information
Product Part No.
AS4C8M32MD2A-25BCN
Org.
8M
x
32
Temperature
-25°C to 85°C
Max Clock (MHz)
400
Package
134-ball FBGA
Table 2. Speed Grade Information
Speed Grade
DDR2L-800
Clock Frequency
RL
400 MHz
6
WL
3
t
RCD
(ns)
18
t
RP
(ns)
18
Confidential
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Rev.1.0 Jun. 2018
AS4C8M32MD2A-25BCN
Figure 3. State Diagram
Power
applied
Power
On
R
es
et
DPDX
Deep
Power
Down
Self
Refreshing
Automatic Sequence
Command Sequence
Resetting
MR
Reading
MRR
Resetting
es
R
DPD
PD
X
PD
EF
X
SR
REF
S
et
Resetting
Power
Down
Idle
MR
Reading
Idle
*1
MR
R
REF
Refreshing
MR
W
PD
X
PD
MR
Writing
ACT
Idle
Power
Down
PR
Active
Power
Down
PD
PD
X
Active
MR
Reading
MR
R
BST
WR
PR(A) = Precharge (All)
ACT = Activate
Writing
WR(A) = Write (with Auto precharge)
RD(A) = Read (with Auto precharge)
BST = Burst Terminate
Reset = Reset is achieved through MRW command
MRW = Mode Register Write
WRA
MRR = Mode Register Read
PD = Enter Power Down
PDX = Exit Power Down
SREF = Enter Self Refresh
Writing
SREFX = Exit Self Refresh
With
DPD = Enter Deep Power Down
Auto precharge
DPDX = Exit Deep Power Down
REF = Refresh
Active
BST
RD
WR
RD
Reading
RA
RD
W
A
PR, PRA
RDA
Auto precharge
Reading
With
Precharging
NOTE 1. All banks are precharged in the idle state.
Confidential
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Rev.1.0 Jun. 2018
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