AT25M02
SPI Serial EEPROM
2-Mbit (262,144 x 8)
DATASHEET
Features
Low-voltage and Standard-voltage Operation Available
̶
̶
1.7V (V
CC
= 1.7V to 5.5V)
2.5V (V
CC
= 2.5V to 5.5V)
Serial Peripheral Interface (SPI) Compatible Interface
Supports SPI Modes 0 (0,0) and 3 (1,1)
High Speed Operation
̶
̶
̶
5MHz Clock Rate from 1.7V to 5.5V
Partial Page Writes Allowed
Byte Write Operation Supported
̶
All Write Operations Complete Within 10ms Max
̶
Ability to Protect the Upper Quarter, Upper Half, or the Entire Memory Array
̶
Write Protect (WP) Pin and Write Disable instructions for Both Hardware and
Software Data Protection
̶
̶
Endurance: 1,000,000 Write Cycles
Data Retention: 40 Years
̶
8-lead JEDEC SOIC and 8-ball Thin WLCSP
̶
Wafer form, Waffle Pack, and Bumped Die Available
256-byte Page Write Mode Support
Self-timed Write Cycle
Block Write Protection
Multiple Write Protection Methods
High Reliability
Green Package Options (Lead-free/Halide-free/RoHS Compliant)
Die Sale Options
Description
The Atmel
®
AT25M02 provides 2,097,152 bits of Serial Electrically Erasable
Programmable Read-Only Memory (EEPROM) organized as 262,144 words of
8 bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation is essential. The device
is available in space saving 8-lead JEDEC SOIC and 8-ball Thin WLCSP
packages. In addition, the device operates from 1.7V to 5.5V.
The AT25M02 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed and a
separate erase cycle is not required before writing to the device.
Atmel-8832C-SEEPROM-AT25M02-Datasheet_012017
Ta b le of C o nte nts
1.
2.
3.
Pin Configurations and Pinouts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device Block Diagram and Bus Connections
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Device Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
3.2
3.3
3.4
Interfacing the AT25M02 on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hold Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
6
6
4.
Device Commands and Addressing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
4.2
Status Register Bit Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read Status Register (RDSR) and Low Power Write Poll (LPWP). . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.1
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2.2
Low Power Write Poll (LPWP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Enable (WREN) and Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3.1
Write Enable Instruction (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3.2
Write Disable Instruction (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.1
Block Write Protect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4.2
Write Protect Enable Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3
4.4
5.
6.
Read Array Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Commands
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1
6.2
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1
Internal Writing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2
Polling Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
14
7.
Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC and AC Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Cell Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Requirements, Reset, and Default Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.3
Device Default State at Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.4
Device Default Condition from Atmel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
17
18
18
18
18
19
19
19
8.
9.
Ordering Code Detail
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ordering Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. Part Marking Scheme
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11. Packaging Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11.1
11.2
8S1 — 8-lead JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8U-10 — 8-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12. Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
AT25M02 [DATASHEET]
Atmel-8832C-SEEPROM-AT25M02-Datasheet_012017
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Description
Asserted
State
Pin
Type
Pin
Pin
Number Symbol Pin Name and Functional Description
Chip Select:
Asserting the CS pin selects the device. When the CS pin is
deasserted, the device will be deselected and placed in standby mode and the
SO pin will be in a high impedance state. When the device is deselected, data
will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation and a
low-to-high transition is required to end an operation. When ending the
internally self-timed write cycle, the device will not enter the standby mode until
the completion of the operation.
Serial Data Output:
The SO pin is used to shift data out from the device. Data
on the SO pin is always clocked out on the falling edge of SCK. The SO pin will
be in a high impedance state whenever the device is deselected (CS is
deasserted).
Write Protect:
The Write Protect (WP) pin is used in conjunction with the block
protection bits of the Status Register (see
Table 4-3 on page 10)
to inhibit
writing to a portion of, or the entire memory array.
The WP pin can also be used in conjunction with the WPEN bit to prevent
inadvertent writing to the Status Register (see
Table 4-4 on page 11).
The
protection is invoked by driving the WP pin to a low state.
Ground:
The ground reference for the device power supply (V
CC
). GND should
be connected to the system ground.
Serial Data Input:
Instructions, addresses and data are latched by the
AT25M02 on the rising edge of the Serial Clock (SCK) line via the Serial Data
Input (SI) pin.
Serial Clock:
The Serial Clock (SCK) pin is used to provide a clock to the
device and is used to synchronize the flow of data to and from the device.
Instructions, addresses and data present on SI pin are always latched in on the
rising edge of SCK, while output data on the SO pin is always clocked out on
the falling edge of SCK.
Hold:
When the device is selected and a serial sequence is underway, Hold can
be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low
while the SCK pin is low. To resume serial communication, the HOLD pin is
brought high while the SCK pin is low (SCK may still toggle during Hold). Inputs
to the SI pin will be ignored and the SO pin will be in a high impedance state.
Device Power Supply:
The V
CC
pin is used to supply the source voltage to the
device. Operations at invalid V
CC
voltages may produce spurious results and
should not be attempted.
1
CS
Low
Input
2
SO
—
Output
3
WP
Low
Input
4
GND
—
Power
5
SI
—
Input
6
SCK
—
Input
7
HOLD
Low
Input
8
V
CC
—
Power
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball WLCSP
V
CC
HOLD
SCK
SI
V
CC
HOLD
SCK
SI
6
5
4
8
7
1
2
CS
SO
WP
GND
Note: Drawings are not to scale.
3
Top View
Top View
AT25M02 [DATASHEET]
Atmel-8832C-SEEPROM-AT25M02-Datasheet_012017
3
2.
Device Block Diagram and Bus Connections
Figure 2-1.
Block Diagram
CS
High Voltage
Generation Circuit
Status Register
Memory
System Control
Module
Power
On Reset
Generator
V
CC
EEPROM Array
Full Array WP Range
1 page
Half Array WP Range
Row Decoder
SO
(256 bytes per page x 1024 pages)
Suspend
Operation
Control
HOLD
Quarter Array WP Range
Address Register
and Counter
WP
Column Decoder
Data Register
SCK
Data Output
Buffer
GND
Write
Protection
Control
SI
Figure 2-2.
SPI Bus Master Connections to Serial EEPROMs
SPI Master:
Microcontroller
Serial Clock (SPI CK)
Data Out (MISO)
Data In (MOSI)
SI
SO SCK
SI
SO SCK
SI
SO SCK
SI
SO SCK
Slave 0
AT25xxx
SS3 SS2 SS1 SS0
CS
Slave 1
AT25xxx
CS
Slave 2
AT25xxx
CS
Slave 3
AT25xxx
CS
4
AT25M02 [DATASHEET]
Atmel-8832C-SEEPROM-AT25M02-Datasheet_012017
3.
Device Operation
The AT25M02 is controlled by a set of instructions that are sent from a host controller, commonly referred to as
the SPI Master. The SPI Master communicates with the AT25M02 via the SPI bus which is comprised of four
signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus.
The AT25M02 supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3, data is
always latched in on the rising edge of SCK and always output on the falling edge of SCK. The only difference
between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is
in standby mode and not transferring any data). SPI Mode 0 is defined as a low SCK while CS is not asserted
(at V
CC
) and SPI Mode 3 has SCK high in the inactive state. The SCK idle state must match when the CS is
deasserted both before and after the communication sequence in SPI Mode 0 and 3. The figures in this
document depict Mode 0 with a solid line on SCK while CS is inactive and Mode 3 with a dotted line.
Figure 3-1.
CS
Mode 3
Mode 3
SPI Mode 0 and Mode 3
SCK
Mode 0
Mode 0
SI
MSB
LSB
SO
MSB
LSB
3.1
Interfacing the AT25M02 on the SPI Bus
Communication to and from the AT25M02 must be initiated by the SPI Master device, such as a microcontroller.
The SPI Master device must generate the serial clock for the AT25M02 on the SCK pin. The AT25M02 always
operates as a slave due to the fact that the Serial Clock pin (SCK) is always an input.
Selecting the Device:
The AT25M02 is selected when the CS pin is low. When the device is not selected, data
will not be accepted via the SI pin, and the SO pin will remain in a high impedance state.
Sending Data to the Device:
The AT25M02 uses the Serial Data Input (SI) pin to receive information. All
instructions, addresses and data input bytes are clocked into the device with the Most Significant Bit (MSB) first.
The SI pin samples on the first rising edge of the SCK line after the CS has been asserted.
Receiving Data from the Device:
Data output from the device is transmitted on the Serial Data Output (SO)
pin, with the MSB output first. The SO data is latched on the first falling edge of SCK after the instruction has
been clocked into the device, such as the Read from Memory Array and Read Status Register instructions. See
Section 5. “Read Array Operation” on page 12
for more details.
3.2
Device Opcodes
Serial Opcode:
After the device is selected by driving CS low, the first byte will be received on the SI pin. This
byte contains the opcode that defines the operation to be performed. Please refer to
Table 4-1 on page 7
for a
list of all opcodes that the AT25M02 will respond to.
Invalid Opcode:
If an invalid opcode is received, no data will be shifted into AT25M02 and the Serial Data
Output (SO) pin will remain in a high impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
AT25M02 [DATASHEET]
Atmel-8832C-SEEPROM-AT25M02-Datasheet_012017
5
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