Changes to Ordering Guide .......................................................... 24
Added to Automotive Products Section ...................................... 24
12/08—Rev. A to Rev. B
Changes to ESD Parameter, Table 3 ............................................... 6
Changes to Ordering Guide .......................................................... 24
8/05—Rev. 0 to Rev. A
Update Format .................................................................... Universal
Change to Table 1 ............................................................................. 3
Change to Table 3 ............................................................................. 6
Change to Reference Section......................................................... 16
Changes to Ordering Guide .......................................................... 24
11/02—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
SPECIFICATIONS
AV
DD
= V
DRIVE
= 2.7 V to 5.25 V, REF
IN
= 2.5 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
2
B Version
1
70
69
69
70
−77
−73
−78
−76
−90
−90
10
50
−85
8.2
1.6
12
±1
−0.9/+1.5
±8
±0.5
±1.5
±0.5
Unit
dB min
dB min
dB min
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
dB typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
f
IN
= 50 kHz sine wave, f
SCLK
= 20 MHz
@ 5 V, –40°C to +85°C
@ 5 V, 85°C to 125°C, typ 70 dB
@ 3 V typ 70 dB, –40°C to +125°C
@ 5 V typ, −84 dB
@ 3 V typ,−77 dB
@ 5 V typ, −86 dB
@ 3 V typ, −80 dB
f
A
= 40.1 kHz, f
B
= 41.5 kHz
AD7923
Signal-to-Noise (SNR)
2
Total Harmonic Distortion (THD)
2
Peak Harmonic or Spurious Noise
(SFDR)
2
Intermodulation Distortion (IMD)
2
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation
Full Power Bandwidth
DC ACCURACY
2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REF
IN
Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 × REF
IN
Input Range
Positive Gain Error
Positive Gain Error Match
Zero-Code Error
Zero-Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REF
IN
Input Voltage
DC Leakage Current
REF
IN
Input Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN 3
f
IN
= 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Straight binary output coding
Typ ±0.5 LSB
−REF
IN
to +REF
IN
biased about REF
IN
with twos
complement output coding
±1.5
±0.5
±8
±0.5
±1
±0.5
0 to REF
IN
0 to 2 × REF
IN
±1
20
2.5
±1
36
0.7 × V
DRIVE
0.3 × V
DRIVE
±1
10
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
µA max
pF typ
V
µA max
kΩ typ
V min
V max
µA max
pF max
Rev. D | Page 3 of 24
Typ ±0.8 LSB
Range bit set to 1
Range bit set to 0, AV
DD
= 4.75 V to 5.25 V
±1% specified performance
f
SAMPLE
= 200 kSPS
Typ 10 nA, V
IN
= 0 V or V
DRIVE
AD7923
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
3
Output Coding
B Version
1
V
DRIVE
– 0.2
0.4
±1
10
Twos Complement
Straight (Natural)
Binary
Unit
V min
V max
µA max
pF max
Test Conditions/Comments
Data Sheet
I
SOURCE
= 200 µA, AV
DD
= 2.7 V to 5.25 V
I
SINK
= 200 µA
Coding bit set to 0
Coding bit set to 1
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
AV
DD
V
DRIVE
I
DD 4
During Conversion
Normal Mode (Static)
Normal Mode (Operational) f
SAMPLE
= 200 kSPS
Using Auto Shutdown Mode f
SAMPLE
= 200 kSPS
Auto Shutdown (Static)
Full Shutdown Mode
Power Dissipation
4
Normal Mode (Operational) f
SAMPLE
= 200 kSPS
Auto Shutdown (Static)
Full Shutdown Mode
800
300
300
200
2.7/5.25
2.7/5.25
2.7
2.0
600
1.5
1.2
900
650
0.5
0.5
7.5
3.6
2.5
1.5
2.5
1.5
ns max
ns max
ns max
kSPS max
V min/max
V min/max
mA max
mA max
µA typ
mA max
mA max
µA typ
µA typ
µA max
µA max
mW max
mW max
µW max
µW max
µW max
µW max
16 SCLK cycles with SCLK at 20 MHz
Sinewave input
Full-scale step Input
See Serial Interface section
Digital I/Ps = 0 V or V
DRIVE
AV
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
AV
DD
= 2.7 V to 5.25 V, SCLK on or off
AV
DD
= 4.75 V to 5.25 V, f
SCLK
= 20 MHz
AV
DD
= 2.7 V to 3.6 V, f
SCLK
= 20 MHz
AV
DD
= 4.75 V to 5.25 V, f
SAMPLE
= 200 kSPS
AV
DD
= 2.7 V to 3.6 V, f
SAMPLE
= 200 kSPS
SCLK on or off (20 nA typ)
SCLK on or off (20 nA typ)
AV
DD
= 5 V, f
SCLK
= 20 MHz
AV
DD
= 3 V, f
SCLK
= 20 MHz
AV
DD
= 5 V
AV
DD
= 3 V
AV
DD
= 5 V
AV
DD
= 3 V
Temperature range: B Version:
−40°C
to +125°C.
See Terminology section.
3
Sample tested @ 25°C to ensure compliance.
4
See Power vs. Throughput Rate section.
1
2
Rev. D | Page 4 of 24
Data Sheet
TIMING SPECIFICATIONS
AV
DD
= 2.7 V to 5.25 V, V
DRIVE
≤ AV
DD
, REF
IN
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Parameter
f
SCLK 2
t
CONVERT
t
QUIET
t
2
t
3 3
t
4 3
t
5
t
6
t
7
t
8 4
t
9
t
10
t
11
t
12
1
AD7923
Limit at T
MIN
, T
MAX
AV
DD
= 3 V
AV
DD
= 5 V
Unit
10
10
kHz min
20
20
MHz max
16 × t
SCLK
16 × t
SCLK
50
50
ns min
10
35
40
0.4 × t
SCLK
0.4 × t
SCLK
10
15/45
10
5
20
1
10
30
40
0.4 × t
SCLK
0.4 × t
SCLK
10
15/35
10
5
20
1
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
µs max
Description
Minimum quiet time required between CS rising edge and start of next
conversion
CS to SCLK set-up time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Sixteenth SCLK falling edge to CS high
Power-Up time from full power-down/auto shutdown mode
Sample tested at 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of AV
DD
) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
The mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
DRIVE
.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t
8
, is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
03086-002
Figure 2. Load Circuit for Digital Output Timing Specification
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