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CY7C1361KVE33-100AXE

Description
static random access memory
Categorysemiconductor    Memory IC    Static random access memory   
File Size578KB,23 Pages
ManufacturerCypress Semiconductor
Environmental Compliance
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CY7C1361KVE33-100AXE Overview

static random access memory

CY7C1361KVE33-100AXE Parametric

Parameter NameAttribute value
MakerCypress Semiconductor
Product Categorystatic random access memory
EncapsulationTray
seriesCY7C1361KVE33
Factory packaging quantity72
CY7C1361KVE33
9-Mbit (256K × 36) Flow-Through SRAM
9-Mbit (256K × 36) Flow-Through SRAM
Features
Functional Description
The CY7C1361KVE33 is a 3.3 V, 256K × 36 synchronous
flow-through SRAMs, respectively designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE
1
), depth-expansion chip enables (CE
2
and
CE
3
), burst control inputs (ADSC, ADSP, and ADV), write
enables (BW
x
, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1361KVE33 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1361KVE33 operates from a +3.3 V core power
supply while all outputs may operate with either a +2.5 or +3.3 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click
here.
Supports 133 MHz bus operations
256K × 36 common I/O
3.3 V – 5% and +10% core power supply (V
DD
)
2.5 V or 3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
6.5 ns (133-MHz version)
Provide high performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
Selection Guide
Description
Maximum access time
Maximum operating current
133 MHz
6.5
149
Unit
ns
mA
Cypress Semiconductor Corporation
Document Number: 002-12709 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised January 4, 2018

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