LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
CMOS SyncFIFO
™
64 x 9, 256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
IDT72421, IDT72201
IDT72211, IDT72221
IDT72231, IDT72241
IDT72251
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64 x 9-bit organization (IDT72421)
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1,024 x 9-bit organization (IDT72221)
2,048 x 9-bit organization (IDT72231)
4,096 x 9-bit organization (IDT72241)
8,192 x 9-bit organization (IDT72251)
10 ns read/write cycle time
Read and Write Clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set
to any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in the 32-pin plastic leaded chip carrier (PLCC) and
32-pin Thin Quad Flat Pack (TQFP)
For through-hole product please see the IDT72420/72200/72210/
72220/72230/72240 data sheet
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. These devices have a 64, 256, 512, 1,024,
2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are
applicable for a wide variety of data buffering needs such as graphics, local area
networks and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when
the write enable pins are asserted. The output port is controlled by another clock
pin (RCLK) and two read enable pins (REN1,
REN2).
The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An output enable pin
(OE) is provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for
PAE
and
PAF,
respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the load pin (LD).
These FIFOs are fabricated using high-speed submicron CMOS technology.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
D
0
- D
8
LD
INPUT REGISTER
OFFSET REGISTER
EF
PAE
PAF
FF
WRITE CONTROL
LOGIC
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
Q
0
- Q
8
2655 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2017
NOVEMBER 2017
DSC-2655/7
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
RS
D
2
D
3
D
5
D
6
D
4
D
2
D
3
D
4
D
5
D
6
D
7
INDEX
D
8
32 31 30 29 28 27 26 25
4
D
1
5
6
7
8
9
10
11
12
13
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
14 15 16 17 18 19 20
Q
1
Q
2
EF
Q
3
Q
4
2655 drw 02
OE
EF
FF
Q
0
Q
1
Q
3
Q
2
Q
4
FF
Q
0
D
7
D
8
INDEX
2655 drw02a
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
D
0
-D
8
Data Inputs
RS
Reset
WCLK
WEN1
Write Clock
Write Enable 1
WEN2/
LD
Write Enable 2/
Load
Q
0
-Q
8
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF
Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
V
CC
GND
©
I/O
Description
I Data inputs for a 9-bit bus.
I When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
I If the FIFO is configured to have programmable flags,
WEN1
is the only write enable pin. When
WEN1
is LOW,
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables,
WEN1
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the
FF
is LOW.
I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/
LD
is
HIGH
at reset, this pin operates as a second write enable. If WEN2/
LD
is LOW at reset, this pin operates as a control
to load and read the programmable flag offsets. If the FIFO is configured to have two write enables,
WEN1
must
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the
FF
is
LOW. If the FIFO is configured to have programmable flags, WEN2/
LD
is held LOW to write or read the
programmable flag offsets.
O Data outputs for a 9-bit bus.
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1
and
REN2
are asserted.
I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
I When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
O When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is HIGH, the
FIFO is not empty.
EF
is synchronized to RCLK.
O When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is Empty+7.
PAE
is synchronized to RCLK.
O When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is Full-7.
PAF
is synchronized to WCLK.
O When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO
is not full.
FF
is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
Com'l & Ind'l
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
T
A
T
A
Parameter
Supply Voltage
Commercial/Industrial
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
4.5
0
2.0
—
0
–40
Typ. Max.
5.0
5.5
0
—
—
—
—
0
—
0.8
+70
+85
Unit
V
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C)
IDT72421
IDT72201
IDT72211
IDT72221
IDT72231
IDT72241
Com'l and Ind'l
(1)
t
CLK
= 10, 15, 25 ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
—
—
1
10
—
0.4
35
5
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4,7)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2mA
Output Logic “0” Voltage, I
OL
= 8mA
Active Power Supply Current
Standby Current
IDT72251
Com'l and Ind'l
(1)
t
CLK
= 10, 15, 25 ns
Min.
Typ.
Max.
–1
–10
2.4
—
—
—
—
—
—
—
—
—
1
10
—
0.4
50
5
Unit
μA
μA
V
V
mA
mA
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Measurements with 0.4
≤
V
IN
≤
V
CC
.
3.
OE
≥
V
IH
, 0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs open (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical I
CC1
= 1.7 + 0.7*f
S
+ 0.02*C
L
*f
S
(in mA).
These equations are valid under the following conditions:
V
CC
= 5V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
©
3
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C)
Commercial
IDT72421L10
IDT72201L10
IDT72211L10
IDT72221L10
IDT72231L10
IDT72241L10
IDT72251L10
Min.
Max.
—
100
2
6.5
10
—
4.5
—
4.5
—
3
—
0.5
—
3
—
0.5
—
10
—
8
—
8
—
—
10
0
—
3
6
3
6
—
6.5
—
6.5
—
6.5
—
6.5
5
—
14
—
Com'l & Ind'l
(1)
IDT72421L15
IDT72201L15
IDT72211L15
IDT72221L15
IDT72231L15
IDT72241L15
IDT72251L15
Min.
Max.
—
66.7
2
10
15
—
6
—
6
—
4
—
1
—
4
—
1
—
15
—
10
—
10
—
—
15
0
—
3
8
3
8
—
10
—
10
—
10
—
10
6
—
15
—
Com'l & Ind'l
(1)
IDT72421L25
IDT72201L25
IDT72211L25
IDT72221L25
IDT72231L25
IDT72241L25
IDT72251L25
Min.
Max.
—
40
2
15
25
—
10
—
10
—
6
—
1
—
6
—
1
—
15
—
15
—
15
—
—
25
0
—
3
13
3
13
—
15
—
15
—
15
—
15
10
—
18
—
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable Almost-Full Flag
Read Clock to Programmable Almost-Empty Flag
Skew time between Read Clock & Write Clock for
Empty Flag & Full Flag
Skew time between Read Clock & Write Clock for
Almost-Empty Flag & Programmable Almost-Full Flag
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
5V
1.1K
D.U.T.
680Ω
Max.
10
10
Unit
pF
pF
CAPACITANCE
(Ta = +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
30pF*
2655 drw 03
NOTES:
1. With output deselected (OE
≥
V
IH
).
2. Characterized values, not currently tested.
©
or equivalent circuit
Figure 1. Output Load
*includes jig and scope capacitances
4
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set HIGH at Reset (RS = LOW), this pin
operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock (WCLK). Data is stored in the RAM array sequentially and
independently of any ongoing read operation.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
WFF
, allowing a valid write to begin. Write Enable 1 (WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when the Write Enable
2/Load (WEN2/LD) is set LOW at Reset (RS=LOW). The IDT72421/72201/
72211/72221/72231/72241/72251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when the Write Enable
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set LOW, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOW-
to-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth
transition. The fifth transition of the Write Clock (WCLK) again writes to the Empty
(Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, the Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full flag (PAF) will be reset
to HIGH after t
RSF
. The Empty Flag (EF) and Programmable Almost-Empty
flag (PAE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag
(PAF) are synchronized with respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM array on the LOW-
to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion, there are two enable control pins. See Write Enable 2 paragraph
below for operation in this configuration.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
WFF
, allowing a valid write to begin. Write Enable 1 (WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of RCLK.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLES (REN1,
REN2)
When both Read Enables (REN1,
REN2)
are LOW, data is read from the
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When either Read Enable (REN1,
REN2)
is HIGH, the output register holds
the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after t
REF
and a valid
read can begin. The Read Enables (REN1,
REN2)
are ignored when the FIFO
is empty.
LD
WEN1
WCLK
0
0
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
0
1
1
1
0
1
NOTE:
1. For the purposes of this table, WEN2 = V
IH
.
2. The same selection sequence applies to reading from the registers.
REN1
and
REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
©
5
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